View ST7LITE25F2_8102590.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. june 2013 doc id 8349 rev 5 1/166 1 st7lite20f2 ST7LITE25F2 st7lite29f2 8-bit microcontroller with si ngle voltage flash memory, data eeprom, adc, timers, spi datasheet ? production data features memories ? 8 kbytes single voltage flash program memory with read-out protection ? in-circuit programming and in-application programming (icp and iap) ? 10k write/erase cycles guaranteed ? data retention: 20 years at 55 c ? temperature range: -40c to 105c ? 384 bytes ram. clock, reset and supply management ? enhanced reset system ? enhanced low voltage supervisor (lvd) for main supply and an auxiliary voltage detector (avd) with interrupt capability for implementing safe power-down procedures ? clock sources: intern al 1% rc oscillator, crystal/ceramic resonato r or external clock ? internal 32-mhz input clock for auto-reload timer ? optional x4 or x8 pll for 4 or 8 mhz internal clock ? five power saving modes: halt, active-halt, wait and slow, auto-wakeup from halt. i/o ports ? up to 15 multifunctional bidirectional i/o lines ? 7 high sink outputs. 4 timers ? configurable watchdog timer ? two 8-bit lite timers with prescaler ? 1 real-time base and 1 input capture ? one 12-bit auto-reload timer with 4 pwm outputs, input capture and output compare functions. 1 communication interface ? spi synchronous serial interface. interrupt management ? 10 interrupt vectors plus trap and reset ? 15 external interrupt lines (on 4 vectors). a/d converter ? 7 input channels ? fixed gain op-amp ? 13-bit resolution for 0 to 430 mv (@ 5 v v dd ) ? 10-bit resolution for 430 mv to 5 v (@ 5 v v dd ). instruction set ? 8-bit data manipulation ? 63 basic instructions with illegal opcode detection ? 17 main addressing modes ? 8 x 8 unsigned multiply instructions. development tools ? full hardware/software development package ? dm (debug module) dip20 so20 300? www.st.com
contents st7lite20f2 st 7lite25f2 st7lite29f2 2/166 doc id 8349 rev 5 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.1 in-circuit programming (icp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.2 in-application programming (iap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.1 read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.2 flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.5 access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.6 data eeprom read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
st7lite20f2 st7lite25f 2 st7lite29f2 contents doc id 8349 rev 5 3/166 7 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 internal rc oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.5.2 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.5.3 external power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.5.4 internal low voltage detector (lvd) reset . . . . . . . . . . . . . . . . . . . . . . 39 7.5.5 internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.6 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.6.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.6.2 auxiliary voltage detector (avd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.6.3 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.6.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.4 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.4.1 halt mode recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.5 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.6 auto-wakeup from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.6.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
contents st7lite20f2 st 7lite25f2 st7lite29f2 4/166 doc id 8349 rev 5 10.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.4 unused i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.7 device-specific i/o port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.1.4 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.1.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.1.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2 12-bit autoreload timer 2 (at2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.2.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.2.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.3 lite timer 2 (lt2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.3.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.3.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.3.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.4.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.4.4 clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.4.5 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.4.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
st7lite20f2 st7lite25f 2 st7lite29f2 contents doc id 8349 rev 5 5/166 11.4.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.5 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.5.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.5.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.5.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.1.4 indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.2.1 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.3.2 operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . 121 13.3.3 auxiliary voltage detector (avd) thresholds . . . . . . . . . . . . . . . . . . . . . 122 13.3.4 internal rc oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.5.1 crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 129 13.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
contents st7lite20f2 st 7lite25f2 st7lite29f2 6/166 doc id 8349 rev 5 13.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.7.1 functional ems (electro magnetic susceptibility) . . . . . . . . . . . . . . . . 131 13.7.2 electro magnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.7.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 132 13.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.10 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 141 13.10.1 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.11 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.11.1 amplifier output offset variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.2 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15 device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.1.1 option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.1.2 option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 15.2 device ordering information and transfer of customer code . . . . . . . . . . 153 15.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 15.4 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 16 important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.1 execution of btjx instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.2 adc conversion spurious results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.3 a/d converter accuracy for first conversion . . . . . . . . . . . . . . . . . . . . . . 161 16.4 negative injection impact on adc accuracy . . . . . . . . . . . . . . . . . . . . . 161 16.5 clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 161 16.6 using pb4 as external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16.7 timebase 2 interrupt in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
st7lite20f2 ST7LITE25F2 st 7lite29f2 list of tables doc id 8349 rev 5 7/166 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2. device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. row definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. data eeprom register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. predefined calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7. st7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 8. cpu clock cycle delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 9. effect of low power modes on si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 10. interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11. flag description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 12. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 13. interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 14. external interrupt i/o pin selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 15. external interrupt i/o pin selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 16. external interrupt i/o pin selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 17. external interrupt i/o pin selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 18. active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 19. awu prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 20. awu register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 table 21. dr value and output pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 22. i/o port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 23. i/o configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 24. effect of low power modes on i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 table 25. i/o port interrupt cont rol/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 table 26. ports pa7:0, pb6:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 27. port configuration (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 28. port configuration (interrupt ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 29. ports where th e external interrupt capabilit y selected using the eisr re gister . . . . . . . . . 69 table 30. i/o port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 31. watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 32. watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 33. effect of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 34. interrupts events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 35. counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 36. register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 37. effect of low power modes on lite timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 table 38. tbxf and icf interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 39. lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 40. wait and halt mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 41. interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 42. spi master mode sck frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 43. spi register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 44. low power modes effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 45. channel selection bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 46. adc clock speed selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 47. adc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9 table 48. addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
list of tables st7lite20f2 ST7LITE25F2 st7lite29f2 8/166 doc id 8349 rev 5 table 49. st7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 0 table 50. inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 51. immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 52. long and short instructions supporting direct, indexed, indirect and indirect indexed addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 table 53. short instructions supporting direct, indexed, indirect and indirect indexed addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 54. relative direct and indirect instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 55. instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 56. instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 57. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 58. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 59. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 60. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 61. power on/power down operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 62. avd thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 63. internal rc oscilla tor and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 64. rc oscillator and pll charac teristics (tested for ta = -40 to +85c) @ vdd = 4.5 to 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 65. rc oscillator and pll characteri stics (tested for ta = -40 to +85c) @ vdd = 2.7 to 3.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 66. 32mhz pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 67. supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 68. on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 69. general timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 70. auto wakeup from halt oscillator (awu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 71. resonator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 72. resonator performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 73. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 74. flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 75. eeprom data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 76. test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 77. emission test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 78. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 79. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 80. general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 81. output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 82. asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 83. serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 84. 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 85. adc accuracy with v dd =5.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 86. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 87. typical offset variation over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 table 88. small outline package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 47 table 89. dual in-line package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 90. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 91. soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . 149 table 92. option bytes values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 93. size definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 94. option byte default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 95. lvd threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 96. list of valid option combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
st7lite20f2 ST7LITE25F2 st 7lite29f2 list of tables doc id 8349 rev 5 9/166 table 97. supported part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 98. st7lite2 fastrom microcontroller option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 99. stmicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 100. st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 101. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
list of figures st7lite20f2 ST7LITE25F2 st7lite29f2 10/166 doc id 8349 rev 5 list of figures figure 1. general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2. 20-pin so package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. 20-pin dip package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. typical icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 6. eeprom block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. data eeprom programmin g flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8. data eeprom write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 9. data eeprom programmin g cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10. cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11. stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12. pll output frequency timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13. clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 figure 14. reset sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 15. reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16. reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17. low voltage detector vs. reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 18. reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 19. using the avd to monitor vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 20. interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 21. power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 22. slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 23. wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 24. halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 25. halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 26. active-halt timing overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 27. active-halt mode flow-chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 28. awuf mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 29. awuf halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 30. awuf mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 31. i/o port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 32. interrupt i/o port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 33. watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 34. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 35. pwm inversion diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 36. pwm function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 37. pwm signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 38. block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 39. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 40. lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 41. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 42. serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 43. single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 44. generic ss timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 45. hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 46. data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 47. clearing the wcol bit (write collision flag) software se quence . . . . . . . . . . . . . . . . . . . . . 98 figure 48. single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9
st7lite20f2 ST7LITE25F2 st 7lite29f2 list of figures doc id 8349 rev 5 11/166 figure 49. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 50. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 51. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 52. fcpu maximum operating frequency versus v dd supply voltage . . . . . . . . . . . . . . . . . . . 121 figure 53. rc osc freq vs vdd @ ta= 25c (calibrat ed with rccr1: 3v @ 25c) . . . . . . . . . . . 124 figure 54. rc osc freq vs vdd (calibrated with rccr0: 5v@ 25c). . . . . . . . . . . . . . . . . . . . . . . 124 figure 55. typical rc oscillator accuracy vs temperature @ vdd=5v (calibrated with rccr0: 5v @ 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 56. rc osc freq vs vdd and rccr value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 57. pll dfcpu/fcpu versus time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 58. pllx4 output vs clkin frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 figure 59. pllx8 output vs clkin frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 figure 60. typical i dd in run vs. f cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 61. typical idd in slow vs. fcpu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 62. typical i dd in wait vs. f cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 63. typical idd in slow-wait vs. fcpu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 64. typical idd in awuf mode at ta= 25c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 65. typical idd vs. temperature at vdd = 5v and fcpu = 8mhz . . . . . . . . . . . . . . . . . . . . . 128 figure 66. typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 67. two typical applications with unused i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 68. typical i pu vs. v dd with v in =v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 69. typical vol at vdd = 2.4v (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 70. typical v ol at v dd = 2.7v (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 71. typical vol at vdd = 3.3v (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 72. typical vol at vdd = 5v (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 figure 73. typical vol at vdd = 2.4v (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 74. typical vol at vdd = 5v (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 figure 75. typical vol at vdd = 3v (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 figure 76. typical vdd-voh at vdd = 2.4v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 figure 77. typical vdd-voh at vdd = 2.7v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 figure 78. typical vdd-voh at vdd = 3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 38 figure 79. typical vdd-voh at vdd=4v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 38 figure 80. typical vdd-voh at vdd=5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 38 figure 81. vol vs. vdd (standard i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 82. typical vol vs. vdd (high-sink i/os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 39 figure 83. typical vdd-voh vs. vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 84. reset pin protection when lvd is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 85. reset pin protection when lvd is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 86. spi slave timing diagram with cpha = 0 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 87. spi slave timing diagram with cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 88. spi master timing diagram (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 89. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 90. adc accuracy characteristics with amplifier disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 91. adc accuracy characteristics with amplifier enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 92. amplifier noise vs voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 93. 20-pin plastic small outline package, 300-mil width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 94. 20-pin plastic dual in-line package, 300-mil width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
description st7lite20f2 ST7LITE25F2 st7lite29f2 12/166 doc id 8349 rev 5 1 description st7lite20f2, ST7LITE25F2 and st7lite29f2 are referred to as st7lite2. the st7lite2 is a member of the st7 microcontroller family. all st7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. the st7lite2 features flash memory with by te-by-byte in-circuit programming (icp) and in-application programm ing (iap) capability. under software control, the st7lite2 device can be placed in wait, slow, or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling th e design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. for easy reference, all parametric data are located in section 15: device configuration . the devices feature an on-chip debug module (dm) to support in-circuit debugging (icd). for a description of the dm registers, refer to the st7 icc protocol reference manual. table 1. device summary features st7lite20f2 ST7LITE25F2 st7lite29f2 program memory - bytes 8 kbyte ram (stack) - bytes 384 (128) data eeprom - bytes ?? 256 peripherals lite timer with watchdog, autoreload timer, spi, 10-bit adc with op-amp lite timer with watchdog, autoreload timer with 32-mhz input clock, spi, 10-bit adc with op-amp operating supply 2.4v to 5.5v cpu frequency up to 8 mhz (w/ ext osc up to 16 mhz) up to 8 mhz (w/ ext osc up to 16 mhz and int 1mhz rc 1% pllx8/4 mhz) operating temperature ?40 c to +85 c packages so20 300?, dip20
st7lite20f2 ST7LITE25F2 st7lite29f2 description doc id 8349 rev 5 13/166 figure 1. general block diagram 8-bit core alu address and data bus osc1 osc2 reset port a internal clock control ram (384 bytes) pa7:0 (8 bits) v ss v dd power supply program (8 kbytes) lvd memory pll x 8 ext. 1 mhz pll int. 1mhz 8-bit lite timer 2 port b spi pb6:0 (7 bits) data eeprom (256 bytes) 1% rc osc to 16 mhz adc + op-amp 12-bit auto-reload timer 2 clkin / 2 or pll x4 8 mhz -> 32 mhz watchdog debug module
pin description st7lite20f2 ST7LITE25F2 st7lite29f2 14/166 doc id 8349 rev 5 2 pin description figure 2. 20-pin so package pinout figure 3. 20-pin dip package pinout legend and abbreviations for device pin description (see table 2 below): ty p e : ? i = input ? o = output ? s = supply in/output level: ?c t = cmos 0.3v dd /0.7v dd with input trigger output level: ? hs = 20ma high sink (on n-buffer only) 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v ss v dd ain5/pb5 clkin/ain4/pb4 mosi/ain3/pb3 miso/ain2/pb2 sck/ain1/pb1 ss /ain0/pb0 osc1/clkin osc2 pa 5 (hs)/atpwm3/iccdata pa 4 (hs)/atpwm2 pa 3 (hs)/atpwm1 pa 2 (hs)/atpwm0 pa 1 (hs)/atic pa 0 (hs)/ltic (hs) 20ma high sink capability eix associated external interrupt vector 12 11 9 10 in/ain6/pb6 pa 7 ( h s ) pa6/mco/iccclk/break reset ei 3 ei2 ei 0 ei 1 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 miso/ain2/pb2 mosi/ain3/pb3 atpwm2/pa4(hs) atpwm3/iccdata/pa5(hs) mco/iccclk/break/pa6 pa 7 ( h s ) ain6/pb6 ain5/pb5 sck/ain1/pb1 ss /ain0/pb0 pa 0 ( h s ) / lt i c osc2 osc1/clkin v ss v dd reset (hs) 20ma high sink capability eix associated external interrupt vector 12 11 9 10 atpwm1/pa3(hs) pa 2 ( h s ) / at p w m 0 pa 1 ( h s ) / at i c clkin/ain4/pb4 ei3 ei3 ei2 ei1 ei0 ei0
st7lite20f2 ST7LITE25F2 st 7lite29f2 pin description doc id 8349 rev 5 15/166 port and control configuration: input: ? float = floating, wpu = weak pull-up, int = interrupt, ana = analog output: ? od = open drain ? pp = push-pull the reset configuration of each pin is shown in bold which is valid as long as the device is in reset state. table 2. device pin description pin no. pin name type level port / control main function (after reset) alternate function so20 dip20 input output input output float wpu int ana od pp 116v ss s ? ? ???? ? ? ground 217v dd s ? ? ???? ? ? main power supply 3 18 reset i/o c t ?? x ?? x ? top priority non maskable interrupt (active low) 4 19 pb0/ain0/ss i/o c t x ei3 xxx port b0 adc analog input 0 or spi slave select (active low) (1) 5 20 pb1/ain1/sck i/o c t x xxx port b1 adc analog input 1 or spi serial clock (1) 6 1 pb2/ain2/miso i/o c t x xxx port b2 adc analog input 2 or spi master in/ slave out data 7 2 pb3/ain3/mosi i/o c t x ei2 xxx port b3 adc analog input 3 or spi master out / slave in data 8 3 pb4/ain4/clkin i/o c t x xxx port b4 adc analog input 4 or external clock input 9 4 pb5/ain5 i/o c t x xxx port b5 adc analog input 5 10 5 pb6/ain6 i/o c t x xxx port b6 adc analog input 6 11 6 pa7 i/o c t hs x ei1 ? xx port a7 ? 12 7 pa 6 / m c o / iccclk/break i/o c t xei1 ? xx port a6 main clock output or in circuit communication clock or external break (2) 13 8 pa5 /atpwm3/ iccdata i/o c t hs x ei1 ? xx port a5 auto-reload timer pwm3 or in circuit communication data 14 9 pa4/atpwm2 i/o c t hs x ? xx port a4 auto-reload timer pwm2 15 10 pa3/atpwm1 i/o c t hs x ei0 ? xx port a3 auto-reload timer pwm1 16 11 pa2/atpwm0 i/o c t hs x ? xx port a2 auto-reload timer pwm0 17 12 pa1/atic i/o c t hs x ? xx port a1 auto-reload timer input capture 18 13 pa0/ltic i/o c t hs x ? xx port a0 lite timer input capture
pin description st7lite20f2 ST7LITE25F2 st7lite29f2 16/166 doc id 8349 rev 5 19 14 osc2 o ?? ???? ? ? resonator oscillator inverter output 20 15 osc1/clkin i ?? ???? ? ? resonator oscillator inverter input or external clock input 1. no negative current injection allowe d on this pin. for details (refer to table 58: current characteristics ). 2. during normal operation this pin must be pulled- up, internally or externally (e xternal pull-up of 10k mandatory in noisy environment). this is to avoid enteri ng icc mode unexpectedly during a reset. in the application, even if the pin is configured as output, any reset wi ll put it back in input pull-up. table 2. device pin description (continued) pin no. pin name type level port / control main function (after reset) alternate function so20 dip20 input output input output float wpu int ana od pp
st7lite20f2 ST7LITE25F2 st7lit e29f2 register & memory map doc id 8349 rev 5 17/166 3 register & memory map as shown in figure 4 , the mcu is able of addressing 64k bytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, 384 bytes of ram, 256 bytes of data eeprom and 8 kbytes of user program memory. the ram space includes up to 128 bytes for the stack from 180h to 1ffh. the highest address bytes contain the user reset and interrupt vectors. the flash memory contains two sectors (see figure 4 ) mapped in the upper part of the st7 addressing space so the reset and interrupt vectors are located in sector 0 (f000h-ffffh). the size of flash sector 0 and other device options are configurable by option byte (refer to section 15: device configuration ). note: memory locations marked as ?reserved? must never be access ed. accessing a reserved area can have unpredictable effects on the device. figure 4. memory map 1. see table 3: hardware register map 2. see table 12: interrupt mapping 3. see section 7.1: internal rc oscillator adjustment 0000h ram flash memory (8k) interrupt hw 0080h 007fh 0fffh 1000h 10ffh ffe0h ffffh 20h reserved 01ffh short addressing ram (zero page) 128 bytes stack 0180h 01ffh 0080h 00ffh (384 bytes) data eeprom (256 bytes) e000h 1100h dfffh reserved ffdfh 16-bit addressing ram 0100h 017fh 1 kbyte 7 kbytes sector 1 sector 0 8k flash ffffh fc00h fbffh e000h program memory 1000h 1001h rccr0 rccr1 (3) ffdeh ffdfh rccr0 rccr1 registers (1) & reset vectors (2) (3)
register & memory map st7lite20f2 ST7LITE25F2 st7lite29f2 18/166 doc id 8349 rev 5 table 3. hardware register map (1) address block register label register name reset status remarks 0000h 0001h 0002h port a pa d r paddr pao r port a data register port a data direction register port a option register ffh (2) 00h 40h r/w r/w r/w 0003h 0004h 0005h port b pbdr pbddr pbor port b data register port b data direction register port b option register ffh (2) 00h 00h r/w r/w r/w (3) 0006h 0007h reserved area (2 bytes) 0008h 0009h 000ah 000bh 000ch lite timer 2 ltcsr2 lta r r ltcntr ltcsr1 lt i c r lite timer control/status register 2 lite timer auto-reload register lite timer counter register lite timer control/status register 1 lite timer input capture register 00h 00h 00h 0x00 0000h 00h r/w r/w read only r/w read only 000dh 000eh 000fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh 0020h 0021h 0022h auto- reload timer 2 at c s r cntrh cntrl at r h at r l pwmcr pwm0csr pwm1csr pwm2csr pwm3csr dcr0h dcr0l dcr1h dcr1l dcr2h dcr2l dcr3h dcr3l at i c r h at i c r l trancr breakcr timer control/status register counter register high counter register low auto-reload register high auto-reload register low pwm output control register pwm 0 control/status register pwm 1 control/status register pwm 2 control/status register pwm 3 control/status register pwm 0 duty cycle register high pwm 0 duty cycle register low pwm 1 duty cycle register high pwm 1 duty cycle register low pwm 2 duty cycle register high pwm 2 duty cycle register low pwm 3 duty cycle register high pwm 3 duty cycle register low input capture register high input capture register low transfer control register break control register 0x00 0000h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 01h 00h r/w read only read only r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w read only read only r/w r/w 0023h to 002dh reserved area (11 bytes) 002eh wdg wdgcr watchdog control register 7fh r/w 0002fh flash fcsr flash control/status register 00h r/w 00030h eeprom eecsr data eeprom c ontrol/status register 00h r/w 0031h 0032h 0033h spi spidr spicr spicsr spi data i/o register spi control register spi control status register xxh 0xh 00h r/w r/w r/w 0034h 0035h 0036h adc adccsr adcdrh adcdrl a/d control status register a/d data register high a/d amplifier control/data low register 00h xxh 0xh r/w read only r/w
st7lite20f2 ST7LITE25F2 st7lit e29f2 register & memory map doc id 8349 rev 5 19/166 0037h itc eicr external interrupt control register 00h r/w 0038h mcc mccsr main clock control/status register 00h r/w 0039h 003ah clock and reset rccr sicsr rc oscillator control register system integrity control/status register ffh 0000 0xx0h r/w r/w 003bh reserved area (1 byte) 003ch itc eisr external interrupt selection register 0ch r/w 003dh to 0048h reserved area (12 bytes) 0049h 004ah awu awupr awucsr awu prescaler register awu control/status register ffh 00h r/w r/w 004bh 004ch 004dh 004eh 004fh 0050h dm (4) dmcr dmsr dmbk1h dmbk1l dmbk2h dmbk2l dm control register dm status register dm breakpoint register 1 high dm breakpoint register 1 low dm breakpoint register 2 high dm breakpoint register 2 low 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w 0051h to 007fh reserved area (47 bytes) 1. legend: x = undefined, r/w = read/write. 2. the contents of the i/o port dr registers are readable only in out put configuration. in input c onfiguration, the values of th e i/o pins are returned instead of the dr register contents. 3. the bits associated with unavailable pi ns must always keep their reset value. 4. for a description of the debug module registers, see icc reference manual. table 3. hardware register map (1) (continued) address block register label register name reset status remarks
flash program memory st7lite2 0f2 ST7LITE25F2 st7lite29f2 20/166 doc id 8349 rev 5 4 flash program memory 4.1 introduction the st7 single voltage extended flash (xflash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. the xflash devices can be programmed off-board (plugged in a programming tool) or on- board using in-circuit programming or in-application programming. the array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features icp (in-circuit programming) iap (in-application programming) ict (in-circuit testing) for downloading and executing user application test patterns in ram sector 0 size configurable by option byte read-out and write protection 4.3 programming modes the st7 can be programmed in three different ways: insertion in a programming tool. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) c an be programmed or erased. in-circuit programming. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) can be pr ogrammed or erased without removing the device from the application board. in-application programm ing. in this mode, sector 1 a nd data eeprom (if present) can be programmed or erased without removing the device from the application board and while the application is running. 4.3.1 in-circuit programming (icp) icp uses a protocol called icc (in-circuit communication) which allows an st7 plugged on a printed circuit board (pcb) to communicate with an external programming device connected via cable. icp is performed in three steps: 1. switch the st7 to icc mode (in-circuit communications). this is done by driving a specific signal sequ ence on the iccclk/data pins while the reset pin is pulled low. when the st7 enters icc mode, it fetches a specific reset vector which points to the st7 system memory containing the icc protocol routine. this routine enables the st7 to receive bytes from the icc interface. 2. download icp driver code in ram from the iccdata pin. 3. execute icp driver code in ram to program the flash memory.
st7lite20f2 ST7LITE25F2 st7l ite29f2 flash program memory doc id 8349 rev 5 21/166 depending on the icp driver code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 in-application programming (iap) this mode uses an iap driver program previously programmed in sector 0 by the user (in icp mode). this mode is fully controlled by user software. this allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.). iap mode can be used to program any memory areas except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.4 icc interface icp needs a minimum of 4 and up to 6 pins to be connected to the programming tool. these pins are: reset : device reset v ss : device power supply ground iccclk: icc output serial clock pin iccdata: icc input serial data pin clkin/pb4: main clock input for external source v dd : application board power supply (optional). if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programmin g tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. refer to the programming tool documentation for recommended resistor values. during the icp session, the progra mming tool must control the reset pin. this can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to isolate the application reset circuit in this case. when using a classical rc network with r>1 k or a reset management ic with open drain output and pull-up resistor > 1 k , no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st programming tools (it is used to monitor the application power supply). please refer to the programming tool manual. pin 9 has to be connected to the clkin/pb4 pin of the st7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. st7 devices with multi-oscillator ca pability need to have osc1 and osc2 grounded in this case. with any programming tool, while the icp option is disabled, the external clock has to be provided on pb4.
flash program memory st7lite2 0f2 ST7LITE25F2 st7lite29f2 22/166 doc id 8349 rev 5 caution: during normal operation the iccclk pin must be pulled up, internally or externally (external pull-up of 10k mandatory in noisy environment). this is to avoid entering icc mode unexpectedly during a reset. in the application, even if the pin is configured as output, any reset will put it back in input pull-up. figure 5. typical icc interface 4.5 memory protection there are two different types of memory protection: read-out protection and write/erase protection which can be applied individually. 4.5.1 read-out protection read-out protection, when selected provides a protection against program memory content extraction and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. both program and data e 2 memory are protected. in flash devices, this protection is removed by reprogramming the option. in this case, both program and data e 2 memory are automatically erased and the device can be reprogrammed. read-out protection selection depends on the device type: in flash devices it is enabled and removed through the fmp_r bit in the option byte. in rom devices it is enabled by mask option specified in the option list. 4.5.2 flash write/erase protection write/erase protection, when set, makes it impossible to both overwrite and erase program memory. it does not apply to e 2 data. its purpose is to provide advanced security to applications and prevent any change being made to the memory content. caution: once set, write/erase protection can never be removed. a write-protected flash device is no longer reprogrammable. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable st7 optional application reset source application i/o (see note 5) clkin/pb4
st7lite20f2 ST7LITE25F2 st7l ite29f2 flash program memory doc id 8349 rev 5 23/166 write/erase protection is enabled through the fmp_w bit in the option byte. 4.6 related documentation for details on flash programming and icc pr otocol, refer to the st7 flash programming reference manual and to the st7 icc protocol reference manual . 4.7 register description flash control/status register (fcsr) read / write reset value: 0000 0000 (00h) 1st rass key: 0101 0110 (56h) 2nd rass key: 1010 1110 (aeh) note: this register is reserved for programming using icp, iap or other programming methods. it controls the xflash programming and erasing operations. when an epb or another programm ing tool is used (in socket or icp mode), the rass keys are sent automatically. 7 0 00000optlatpgm
data eeprom st7lite20f2 st 7lite25f2 st7lite29f2 24/166 doc id 8349 rev 5 5 data eeprom 5.1 introduction the e lectrically e rasable programmable read only memory can be used as a non-volatile backup for storing data. usin g the eeprom requires a basic access protocol described in this chapter. 5.2 main features up to 32 bytes programmed in the same cycle eeprom mono-voltag e (charge pump) chained erase and programming cycles internal control of the global programming cycle duration wait mode management read-out protection figure 6. eeprom block diagram 5.3 memory access the data eeprom memory read/write access modes are controlled by the e2lat bit of the eeprom control/status register (eecsr). the flowchart in figure 7 describes these different memory access modes. eecsr high voltage pump 0 e2lat 0 0 0 0 0 e2pgm eeprom memory matrix (1 row = 32 x 8 bits) address decoder data multiplexer 32 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus
st7lite20f2 ST7LITE25F2 st7lite29f2 data eeprom doc id 8349 rev 5 25/166 read operation (e2lat=0) the eeprom can be read as a normal rom lo cation when the e2lat bit of the eecsr register is cleared. on this device, data eeprom can also be used to execute machine code . take care not to write to the data eeprom while executing from it. this would result in an unexpected code being executed. write operation (e2lat=1) to access the write mode, the e2lat bit has to be set by software (the e2pgm bit remains cleared). when a write access to the eeprom ar ea occurs, the value is latched inside the 32 data latches according to its address. when pgm bit is set by the software, all the prev ious bytes written in the data latches (up to 32) are programmed in the eeprom cells. the effective high address (row) is determined by the last eeprom write sequence. to avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five least significant bits of the address can change. at the end of the programming cycle, the pgm and lat bits are cleared simultaneously. note: care should be taken during the programming cycle. writing to the same memory location will over-program the memory (logical and between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the e2lat bit. it is not possible to read the latched data. this note is illustrated by the figure 9: data eeprom programming cycle . figure 7. data eeprom programming flowchart read mode e2lat=0 e2pgm=0 write mode e2lat=1 e2pgm=0 read bytes in eeprom area writeupto32bytes in eeprom area (with the same 11 msb of the address) start programming cycle e2lat=1 e2pgm=1 (set by software) e2lat 01 cleared by hardware
data eeprom st7lite20f2 st 7lite25f2 st7lite29f2 26/166 doc id 8349 rev 5 figure 8. data eeprom write operation note: if a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. 5.4 power saving modes wait mode the data eeprom can enter wait mode on execution of the wfi instruction of the microcontroller or when the microcontroller enters active-halt mode.the data eeprom will immediately enter this mode if there is no programming in progress, otherwise the data eeprom will finish the cycle an d then enter wait mode. active-halt mode refer to wait mode. halt mode the data eeprom immediately enters halt mo de if the microcontroller executes the halt instruction. ther efore the eeprom will stop the functi on in progress, and data may be corrupted. 5.5 access error handling if a read access o ccurs while e2lat=1, then the data bus will not be driven. if a write access occurs while e2lat=0, th en the data on the bus will not be latched. if a programming cycle is in terrupted (by a reset action), the memory data will not be guaranteed. table 4. row definition ? row / byte ? 0 1 2 3 ... 30 31 physical address 0 00h...1fh 1 20h...3fh ... n nx20h...nx20h+1fh byte 1 byte 2 byte 32 phase 1 programming cycle read operation impossible phase 2 read operation possible e2lat bit e2pgm bit writing data latches waiting e2pgm and e2lat to fall set by user application cleared by hardware
st7lite20f2 ST7LITE25F2 st7lite29f2 data eeprom doc id 8349 rev 5 27/166 5.6 data eeprom read-out protection the read-out protection is enabled through an option bit (see section 15.1: option bytes ). when this option is selected, the programs and data stored in the eeprom memory are protected against read-out (including a re-write protection). in flash devices, when this protection is removed by reprogramming the option byte, the entire program memory and eeprom is first automatically erased. note: both program memory and data eeprom are protected using the same option bit. figure 9. data eeprom programming cycle 5.7 register description eeprom control/status register (eecsr) read/write reset value: 0000 0000 (00h) bits 7:2 = reserved, forced by hardware to 0. bit 1 = e2lat latch access transfer this bit is set by software. it is cleared by hardware at the end of the programming cycle. it can only be cleared by software if the e2pgm bit is cleared. 0: read mode 1: write mode bit 0 = e2pgm programming control and status this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware. 0: programming finished or not yet started 1: programming cycle is in progress note: if the e2pgm bit is cleared during the programming cycle, the memory data is not guaranteed. lat erase cycle write cycle pgm t prog read operation not possible write of data latches read operation possible internal programming voltage 7 0 000000e2late2pgm
data eeprom st7lite20f2 st 7lite25f2 st7lite29f2 28/166 doc id 8349 rev 5 table 5. data eeprom regist er map and reset values address (hex.) register label 76543210 0030h eecsr reset value 000000 e2lat 0 e2pgm 0
st7lite20f2 ST7LITE25F2 st7lite29f2 central processing unit doc id 8349 rev 5 29/166 6 central processing unit 6.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 main features 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes two 8-bit index registers 16-bit stack pointer low power modes maskable hardware interrupts non-maskable software interrupt 6.3 cpu registers the 6 cpu registers shown in figure 10 are not present in the memory mapping and are accessed by specific instructions. figure 10. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value
central processing unit st7lite20f2 ST7LITE25F2 st7lite29f2 30/166 doc id 8349 rev 5 accumulator (a) the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. the cross-assembler generates a precede instruction (pre) to indicate that the following instruction refers to the y register. the y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the interrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop instructions. these bits can be individually tested and/or controlled by specific instructions. bit 4 = h half carry this bit is set by hardware when a carry occurs between bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred 1: a half carry has occurred this bit is tested using the jrh or jrnh instruction. the h bit is useful in bcd arithmetic subroutines. bit 3 = i interrupt mask this bit is set by hardware when entering in interrupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled 1: interrupts are disabled this bit is controlled by the rim, sim and iret instructions and is tested by the jrm and jrnm instructions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptible because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared 7 0 111hinzc
st7lite20f2 ST7LITE25F2 st7lite29f2 central processing unit doc id 8349 rev 5 31/166 by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. bit 2 = n negative this bit is set and cleared by hardware. it is representative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1) this bit is accessed by the jrmi and jrpl instructions. bit 1 = z zero this bit is set and cleared by hardware. this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero 1: the result of the last operation is zero this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow this bit is set and cleared by hardware and software. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred 1: an overflow or underflow has occurred this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. stack pointer register (sp) read/write reset value: 01ffh the stack pointer is a 16-bit register which is always pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 11 ). since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer contains its reset value (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. the previously stored information is then overwritten and therefore lost. the stack also wraps in case of an underflow. 15 8 00000001 7 0 1 sp6 sp5 sp4 sp3 sp2 sp1 sp0
central processing unit st7lite20f2 ST7LITE25F2 st7lite29f2 32/166 doc id 8349 rev 5 the stack is used to save the return address during a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 11 : when an interrupt is received, the sp is decremented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an interrupt five locations in the stack area. figure 11. stack manipulation example pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0180h stack higher address = 01ffh stack lower address = 0180h
st7lite20f2 ST7LITE25F2 st7lite29f2 supply, reset and clock management doc id 8349 rev 5 33/166 7 supply, reset and clock management the device includes a range of utility featur es for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. main features clock management ? 1 mhz internal rc oscillator (enabled by option byte, available on st7lite25 and st7lite29 devices only) ? 1 to 16 mhz or 32khz external crystal/ce ramic resonator (selected by option byte) ? external clock input (enabled by option byte) ? pll for multiplying the frequency by 8 or 4 (enabled by option byte) ? for clock art counter only: pll32 for multiplying the 8 mhz frequency by 4 (enabled by option byte). the 8 mhz input frequency is mandatory and can be obtained in the following ways: . 1 mhz rc + pllx8 . 16 mhz external clock (internally divided by 2) . 2 mhz external clock (internally divided by 2) + pllx8 . crystal oscillator with 16 mhz output frequency (internally divided by 2). reset sequence manager (rsm) system integrity management (si) ? main supply low voltage detection (lvd) with reset generation (enabled by option byte) ? auxiliary voltage detector (avd) with inte rrupt capability for monitoring the main supply (enabled by option byte). 7.1 internal rc oscillator adjustment the device contains an internal rc oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5 v - 5.5 v). it must be calibrated to obtain the frequency required in the application. th is is done by software writing a calibration value in the rccr (rc control register). whenever the microcontroller is reset, the rccr returns to its default value (ffh), i.e. each time the device is reset, the calibration value must be loaded in the rccr. predefined calibration values are stored in eeprom for 3 and 5 v v dd supply voltages at 25 c, as shown in table 6. table 6. predefined calibration values rccr conditions st7lite29 address st7lite25 address rccr0 v dd = 5 v, t a = 25 c, f rc = 1 mhz 1000h and ffdeh ffdeh rccr1 v dd = 3 v, t a = 25 c, f rc = 700 khz 1001h and ffdfh ffdfh
supply, reset and clock management st7lite20f2 ST7LITE25F2 st7lite29f2 34/166 doc id 8349 rev 5 note: see section 13: electrical characteristics for more information on the frequency and accuracy of the rc oscillator. to improve clock stability and frequency accura cy, it is recommended to place a decoupling capacitor, typically 100nf, between the v dd and v ss pins as close as possible to the st7 device. these two bytes are systematically programmed by st, including on fastrom devices. consequently, customers intending to use fastrom service must not use these two bytes. rccr0 and rccr1 calibration values will be eras ed if the read-out pr otection bit is reset after it has been set. see section 4.5.1: read-out protection . caution: if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. refer to application note an1324 for information on how to calibrate the rc frequency using an external reference signal. 7.2 phase locked loop (pll) the pll can be used to multiply a 1 mhz frequ ency from the rc oscilla tor or the external clock by 4 or 8 to obtain f osc of 4 or 8 mhz. the pll is enabled and the multiplication factor of 4 or 8 is selected by 2 option bits. the x4 pll is intended for operation with v dd in the 2.4 v to 3.3 v range the x8 pll is intended for operation with v dd in the 3.3 v to 5.5 v range note: refer to section 15.1: option bytes for the option byte description. if the pll is disabled and the rc oscillator is enabled, then f osc = 1 mhz. if both the rc oscillator and the pll are disabled, f osc is driven by the external clock. figure 12. pll output frequency timing diagram when the pll is started, after reset or wakeup from halt mode or awuf mode, it outputs the clock after a delay of t startup . when the pll output signal reaches the operating frequency, the locked bit in the sicscr register is set. full pll accuracy (acc pll ) is reached after a stabilization time of 4/8 x freq. locked bit set t stab t lock input output freq. t startup t
st7lite20f2 ST7LITE25F2 st7lite29f2 supply, reset and clock management doc id 8349 rev 5 35/166 t stab (see figure 12 below and figure 64: rc oscillator and pll characteristics (tested forta=-40to+85c) @vdd=4.5to 5.5v ). refer to section 7.6.4: register description for a description of the locked bit in the sicsr register. 7.3 register description main clock control/status register (mccsr) read / write reset value: 0000 0000 (00h) bits 7:2 = reserved, must be kept cleared bit 1 = mco main clock out enable this bit is read/write by software and cleared by hardware after a reset. this bit allows to enable the mco output clock. 0: mco clock disabled, i/o port free for general purpose i/o. 1: mco clock enabled. bit 0 = sms slow mode select this bit is read/write by software and cleared by hardware after a reset. this bit selects the input clock f osc2 or f osc2 /32. 0: normal mode (f cpu = f osc2 1: slow mode (f cpu = f osc2 /32) rc control register (rccr) read / write reset value: 1111 1111 (ffh) bits 7:0 = cr[7:0] rc oscillator frequency adjustment bits these bits must be written imm ediately after reset to adjust the rc oscilla tor frequency and to obtain an accuracy of 1%. the application can store the correct value for each voltage range in eeprom and write it to this register at startup. 00h = maximum available frequency ffh = lowest available frequency note: to tune the oscillator, write a serie of diff erent values in the register un til the correct frequency is reached. the fastest method is to use a dichotomy starting with 80h. 7 0 000000mcosms 7 0 cr70 cr60 cr50 cr40 cr30 cr20 cr10 cr0
supply, reset and clock management st7lite20f2 ST7LITE25F2 st7lite29f2 36/166 doc id 8349 rev 5 figure 13. clock management block diagram 7.4 multi-oscillator (mo) the main clock of the st7 can be generated by four different source types coming from the multioscillator block (1 to 16mhz or 32khz): an external source 5 crystal or ceramic resonator oscillators an internal high fr equency rc oscillator. each oscillator is optimized fo r a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in ta bl e 7 . note: refer to section 13: electrical characteristics for more details. external clock source in this external clock mode, a clock signal (s quare, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. cr4 cr7 cr0 cr1 cr2 cr3 cr6 cr5 rccr f osc mccsr sms mco mco f cpu f cpu to cpu and peripherals (1ms timebase @ 8 mhz f osc ) /32 divider f osc f osc /32 f osc f ltimer 1 0 lite timer 2 counter 8-bit at timer 2 12-bit pll 8 mhz -> 32 mhz f cpu clkin osc2 clkin tunable oscillator 1% rc pll 1 mhz -> 8 mhz pll 1 mhz -> 4 mhz rc osc pllx4x8 /2 divider option bits osc,plloff, oscrange[2:0] osc 1-16 mhz or 32 khz clkin clkin /osc1 osc /2 divider osc/2 clkin/2 clkin/2 option bits osc,plloff, oscrange[2:0]
st7lite20f2 ST7LITE25F2 st7lite29f2 supply, reset and clock management doc id 8349 rev 5 37/166 note: when the multi-oscillator is not used, pb4 is selected by default as external clock. crystal/ceramic oscillators this family of oscillators has the advantage of prod ucing a very accurate rate on the main clock of the st7. the selection within a list of 4 oscillators with diff erent frequency ranges has to be done by option byte in order to reduce consumption (refer to section 15.1: option bytes for more details on the frequency ranges). in this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as clos e as possible to the oscillator pins in order to minimize output distorti on and startup stabilizat ion time. the loading capacitance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the reset phase to avoid losing time in the oscillator startup phase. internal rc oscillator in this mode, the tunable 1% rc oscillator is used as main clock source. the two oscillator pins have to be tied to ground. table 7. st7 clock sources clock source hardware configuration external clock crystal/ceramic resonators internal rc oscillator or external clock on pb4 osc1 osc2 external st7 source osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7
supply, reset and clock management st7lite20f2 ST7LITE25F2 st7lite29f2 38/166 doc id 8349 rev 5 7.5 reset sequence manager (rsm) 7.5.1 introduction the reset sequence manager includes three reset sources as shown in figure 15: reset block diagram : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset note: a reset can also be triggered following the detection of an illegal op code or prebyte code. refer to section 12.2.1: illegal opcode reset for further details. these sources act on the reset pin and it is always kept low during the delay phase. the reset service routine vector is fixed at addresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 14 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (see table below) reset vector fetch. the 256 or 4096 cpu clock cycle delay allows the oscillator to stab ilise and ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte: the reset vector fetch phase duration is 2 clock cycles. if the pll is enabled by option byte, it outputs the clock after an additional delay of t startup (see figure 12: pll output frequency timing diagram ). figure 14. reset sequence phases table 8. cpu clock cycle delay clock source cpu clock cycle delay internal rc oscillator 256 external clock (connected to clkin pin) 256 external crystal/ceramic oscillator (connected to osc1/osc2 pins) 4096 reset active phase internal reset 256 or 4096 clock cycles fetch vector
st7lite20f2 ST7LITE25F2 st7lite29f2 supply, reset and clock management doc id 8349 rev 5 39/166 7.5.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in accordance with the input voltage. it can be pulled low by external circuitry to reset the device. note: see section 13: electrical characteristics for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 16: reset sequences ). this detection is asynchronous and therefore the mcu can enter reset state even in halt mode. figure 15. reset block diagram note: see section 12.2.1: illegal opcode reset for more details on illega l opcode reset conditions. the reset pin is an asynchronous sign al which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in section 13: electrical characteristics . 7.5.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specif ied for the selected f osc frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc network connected to the reset pin. 7.5.4 internal low voltag e detector (lvd) reset two different reset sequences ca used by the internal lvd ci rcuitry can be distinguished: power-on reset voltage drop reset. the device reset pin acts as an output that is pulled low when v dd supply, reset and clock management st7lite20f2 ST7LITE25F2 st7lite29f2 40/166 doc id 8349 rev 5 7.5.5 internal watchdog reset the reset sequence generated by a internal watchdog counter overflow is shown in figure 16 . starting from the watchdog co unter underflow, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . figure 16. reset sequences 7.6 system integrity management (si) the system integrity management block contains the low voltage detector (lvd) and auxiliary voltage detector (a vd) functions. it is mana ged by the sicsr register. note: a reset can also be triggered following the detection of an illegal op code or prebyte code. refer to section 12.2.1: illegal opcode reset for further details. 7.6.1 low voltage detector (lvd) the low voltage detector function (lvd) generates a static reset when the v dd supply voltage is below a v it-(lvd) reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it-(lvd) reference value for a voltage drop is lower than the v it+(lvd) reference value for power-on in order to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hysteresis). v dd run reset pin external watchdog active phase v it+(lvd) v it-(lvd) t h(rstl)in run watchdog underflow t w(rstl)out run run reset reset source external reset lvd reset watchdog reset internal reset (256 or 4096 t cpu ) vector fetch active phase active phase
st7lite20f2 ST7LITE25F2 st7lite29f2 supply, reset and clock management doc id 8349 rev 5 41/166 the lvd reset circuitry generates a reset when vdd is below: v it+(lvd) when v dd is rising v it-(lvd) when v dd is falling. the lvd function is illustrated in figure 17 . the voltage threshold can be configured by option byte to be low, medium or high. provided the minimum v dd value (guaranteed for the os cillator frequency) is above v it-(lvd) , the mcu can only be in two modes: under full software control in static safe reset. in these conditions, secure operation is always ensured for the application without the need for external reset hardware. during a low voltage de tector rese t, the reset pin is held low, thus permitting the mcu to reset other devices. note: the lvd allows the device to be us ed without any external reset circuitry. the lvd is an optional function which can be selected by option byte. use of lvd with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull v dd down to 0v to ensure optimum restart conditions. refer to circuit example in figure 84: reset pin protection when lvd is enabled it is recommended to make sure that the v dd supply voltage rises monotonously when the device is exiting from reset, to ensure the application functions properly. figure 17. low voltage detector vs. reset v dd v it+ (lvd) reset v it- (lvd) v hys
supply, reset and clock management st7lite20f2 ST7LITE25F2 st7lite29f2 42/166 doc id 8349 rev 5 figure 18. reset and supply management block diagram 7.6.2 auxiliary voltage detector (avd) the voltage detector function (avd) is ba sed on an analog comparison between a v it-(avd) and v it+(avd) reference value and the v dd main supply voltage (v avd ). the v it-(avd) reference value for falling voltage is lower than the v it+(avd) reference value for rising voltage in order to avoid parasitic detection (hysteresis). the output of the avd comparator is directly readable by the application software through a real time status bit (avdf) in the sicsr register. this bit is read only. note: the avd functions only if the lvd is enabled through the option byte. monitoring the v dd main supply the avd voltage threshold value is relative to the selected lvd threshold configured by option byte (see section 15.1: option bytes ). if the avd interrupt is enabled, an interrupt is generated when the voltage crosses the v it+(lvd) or v it-(avd) threshold (avdf bit is set). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcontroller (see figure 19: using the avd to monitor vdd ). low voltage detector (lvd) auxiliary voltage detector (avd) reset v ss v dd reset sequence manager (rsm) avd interrupt request system integrity management watchdog sicsr timer (wdg) avdie avdf status flag 0 0 lvdrf locked wdgrf 0
st7lite20f2 ST7LITE25F2 st7lite29f2 supply, reset and clock management doc id 8349 rev 5 43/166 figure 19. using the avd to monitor v dd 7.6.3 low power modes interrupts the avd interrupt event generates an interrupt if the corresponding enable control bit (avdie) is set and the interrupt mask in the cc register is reset (rim instruction). v dd v it+(avd) v it-(avd) avdf bit 01 reset if avdie bit = 1 v hyst avd interrupt request interrupt cleared by v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 0 1 hardware interrupt cleared by reset table 9. effect of low power modes on si mode description wait no effect on si. avd interrupts caus e the device to exit from wait mode. halt the sicsr register is fr ozen. the avd remains active. table 10. interrupt control bits interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes no
supply, reset and clock management st7lite20f2 ST7LITE25F2 st7lite29f2 44/166 doc id 8349 rev 5 7.6.4 register description system integrity (si) control/status register (sicsr) read/write reset value: 0000 0xx0 (0xh) bit 7:5 = reserved, must be kept cleared. bit 4 = wdgrf watchdog reset flag this bit indicates that the last reset was generated by the watchdog peripheral. it is set by hardware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, t he flag description is given by the following table: bit 3 = locked pll locked flag this bit is set and cleared by hardware. it is set automatically when the pll reaches its operating frequency. 0: pll not locked 1: pll locked bit 2 = lvdrf lv d r e s e t f l a g this bit indicates that the last reset was generated by the lvd block. it is set by hardware (lvd reset) and cleared by software (by reading). when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 1 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is generated when the avdf bit is set. 0: v dd over avd threshold 1: v dd under avd threshold note: refer to section : monitoring the vdd main supply and to figure 19: using the avd to monitor vdd for additional details. bit 0 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag is set. the pending interrupt information is automatically cleared when software enters the avd interrupt routine. 0: avd interrupt disabled 1: avd interrupt enabled 7 0 0 0 0 wdgrf locked lvdrf avdf avdie table 11. flag description reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lv d 1 x
st7lite20f2 ST7LITE25F2 st7lite29f2 supply, reset and clock management doc id 8349 rev 5 45/166 note: the lvdrf flag is not clea red when another reset type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the original failure. in this case, a watchdog reset can be detected by software while an external reset can not.
interrupts st7lite20f2 ST7LITE25F2 st7lite29f2 46/166 doc id 8349 rev 5 8 interrupts the st7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the interrupt mapping table and a nonmaskable software interrupt (trap). the interrupt processing flowchart is shown in figure 20: interrupt processing flowchart . the maskable interrupts must be enabled by clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see section : external interrupt function ). note: after reset, all interrupts are disabled. when an interrupt has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. the i bit of the cc register is set to prevent additional interrupts. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to table 12: interrupt mapping for vector addresses). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt cannot be interrupted because the i bit is set by hardware entering in interrupt routine. in the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see table 12: interrupt mapping ). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifically mentioned interr upts allow the processor to leave the halt low power mode (refer to the ?exit from halt? column in table 12: interrupt mapping ). 8.1 non maskable software interrupt this interrupt is entered when the trap instruction is executed regardless of the state of the i bit. it will be serviced a ccording to the flowchart on figure 20: interrupt processing flowchart . 8.2 external interrupts external interrupt vectors can be loaded into th e pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to leave the halt low power mode.
st7lite20f2 ST7LITE25F2 st7lite29f2 interrupts doc id 8349 rev 5 47/166 the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt triggered on edge will be latched and th e interrupt request automatically cleared upon entering the interrupt service routine. note: the type of sensitivity defin ed in the miscellaneous or interrupt register (if available) applies to the ei source. in ca se of a nanded source (as described in section 10: i/o ports ), a low level on an i/o pin configured as input with interrupt, masks the interrupt request even in case of rising edge sensitivity. 8.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: the i bit of the cc register is cleared. the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: writing ?0? to the corresponding bit in the status register or access to the status register while the flag is set followed by a read or write of an associated register. note: the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequenc e is executed. figure 20. interrupt processing flowchart i bit set? y n iret? y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n pending?
interrupts st7lite20f2 ST7LITE25F2 st7lite29f2 48/166 doc id 8349 rev 5 table 12. interrupt mapping no. source block description register label priority order exit from halt or awuf exit from active- halt address vector reset reset n/a highest priority lowest priority yes yes fffeh-ffffh trap software interrupt no no fffch-fffdh 0 awu auto-wakeup interrupt awucsr yes (1) fffah-fffbh 1 ei0 external interrupt 0 n/a yes fff8h-fff9h 2 ei1 external interrupt 1 fff6h-fff7h 3 ei2 external interrupt 2 fff4h-fff5h 4 ei3 external interrupt 3 fff2h-fff3h 5 lite timer lite timer rtc2 interrupt ltcsr2 no fff0h-fff1h 6 not used ffeeh-ffefh 7 si avd interrupt sicsr no no ffech-ffedh 8 at timer at timer output compare interrupt or input capture interrupt pwmxcsr or atcsr ffeah-ffebh 9 at timer overflow interrupt atcsr yes ffe8h-ffe9h 10 lite timer lite timer input capture interrupt lt c s r n o f f e 6 h - f f e 7 h 11 lite timer rtc1 interrupt ltcsr yes ffe4h-ffe5h 12 spi spi peripheral interrupts spicsr yes no ffe2h-ffe3h 13 not used ffe0h-ffe1h 1. this interrupt exits the mcu from ?auto-wakeup from halt? mode only.
st7lite20f2 ST7LITE25F2 st7lite29f2 interrupts doc id 8349 rev 5 49/166 external interrupt control register (eicr) read/write reset value: 0000 0000 (00h) bit 7:6 = is3[1:0] ei3 sensitivity these bits define the interrupt sensitivity for ei3 (port b0) according to ta b l e 1 3 : interrupt sensitivity bits . bit 5:4 = is2[1:0] ei2 sensitivity these bits define the interrupt sensitivity for ei2 (port b3) according to ta b l e 1 3 : interrupt sensitivity bits . bit 3:2 = is1[1:0] ei1 sensitivity these bits define the interrupt sensitivity for ei1 (port a7) according to ta b l e 1 3 : interrupt sensitivity bits . bit 1:0 = is0[1:0] ei0 sensitivity these bits define the interrupt sensitivity for ei0 (port a0) according to ta b l e 1 3 : interrupt sensitivity bits . note: these 8 bits can be written only when the i bit in the cc register is set. changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts. refer to section : external interrupt function . 7 0 is31 is30 is21 is20 is11 is10 is01 is00 table 13. interrupt sensitivity bits isx1 isx0 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge
interrupts st7lite20f2 ST7LITE25F2 st7lite29f2 50/166 doc id 8349 rev 5 external interrupt selection register (eisr) read/write reset value: 0000 1100 (0ch) bits 7:6 = ei3[1:0] ei3 pin selection these bits are written by software. they select the port b i/o pin used for the ei3 external interrupt according to the table below. bits 5:4 = ei2[1:0] ei2 pin selection these bits are written by software. they select the port b i/o pin used for the ei2 external interrupt according to the table below. bit 3:2 = ei1[1:0] ei1 pin selection these bits are written by software. they select the port a i/o pin used for the ei1 external interrupt according to the table below. 7 0 is31 is30 is21 is20 is11 is10 is01 is00 table 14. external interrupt i/o pin selection ei31 ei30 i/o pin 0 0 pb0 (1) 1. reset state 0 1 pb1 1 0 pb2 table 15. external interrupt i/o pin selection ei21 ei20 i/o pin 0 0 pb3 (1) 1. reset state 0 1 pb4 (2) 2. pb4 cannot be used as an external interrupt in halt mode. 1 0 pb5 1 1 pb6
st7lite20f2 ST7LITE25F2 st7lite29f2 interrupts doc id 8349 rev 5 51/166 bits 1:0 = ei0[1:0] ei0 pin selection these bits are written by software. they select the port a i/o pin used for the ei0 external interrupt according to the table below. table 16. external interrupt i/o pin selection ei11 ei10 i/o pin 00 pa4 01 pa5 10 pa6 11 pa7 (1) 1. reset state table 17. external interrupt i/o pin selection ei01 ei00 i/o pin 00 pa0 (1) 1. reset state 01 pa1 10 pa2 11 pa3
power saving modes st7lite20f2 ST7LITE25F2 st7lite29f2 52/166 doc id 8349 rev 5 9 power saving modes 9.1 introduction to give a large measure of flexibility to the ap plication in terms of power consumption, five main power saving modes are implemented in the st7 (see figure 21 ): slow wait (and slow-wait) active halt auto wake up from halt (awuf) halt after a reset the normal operat ing mode is selected by defa ult (run mode). this mode drives the device (cpu and embedded periphera ls) by means of a master clock which is based on the main osc illator frequency divided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instructi on whose action depends on the oscillator status. figure 21. power saving mode transitions 9.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device, to adapt the internal clock frequency (f cpu ) to the available supply voltage. power consumption wait slow run active-halt high low slow-wait auto-wakeup from halt halt
st7lite20f2 ST7LITE25F2 st7lite29f2 power saving modes doc id 8349 rev 5 53/166 slow mode is controlled by the sms bit in the mccsr register which enables or disables slow mode. in this mode, the oscillator fr equency is divided by 32. the cpu and peripherals are clocked at this lower frequency. note: slow-wait mode is activated when entering wait mode while the device is already in slow mode. figure 22. slow mode clock transition 9.3 wait mode wait mode places the mcu in a low power consumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i bit of the cc register is cleared, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 23 . sms f cpu normal run mode request f osc f osc /32 f osc
power saving modes st7lite20f2 ST7LITE25F2 st7lite29f2 54/166 doc id 8349 rev 5 figure 23. wait mode flowchart 1. before servicing an interrupt, the cc register is pus hed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. 9.4 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the "halt? instruction w hen activve-halt is disabled (see section 9.5: active-halt mode for more details) and when the awuen bit in the awucsr register is cleared. the mcu can exit halt mode on receptio n of either a specific interrupt (see table 12: interrupt mapping ) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and t he 256 or 4096 cpu cycl e delay is used to stabilize the oscillator. after th e startup delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 25: halt mode flowchart ). when entering halt mode, the i bit in the cc register is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in halt mode, the main oscillator is turned off causing all internal pr ocessing to be stopped, including the operation of the on-chip peripherals. all peripherals are not clocked except the wfi instruction reset interrupt y n n y cpu oscillator peripherals ibit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off 0 on cpu oscillator peripherals ibit on on x (1) on cycle delay 256 or 4096 cpu clock
st7lite20f2 ST7LITE25F2 st7lite29f2 power saving modes doc id 8349 rev 5 55/166 ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). the compatibility of wa tchdog operation with halt mode is configured by the ?wdghalt? option bit of the option byte. the halt instruction when executed while the watchdog system is enabled, can gener ate a watchdog reset (see section 15.1: option bytes for more details). figure 24. halt timing overview halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [active-halt disabled]
power saving modes st7lite20f2 ST7LITE25F2 st7lite29f2 56/166 doc id 8349 rev 5 figure 25. halt mode flowchart 1. wdghalt is an option bit (see section 15.1: option bytes for more details). 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 12: interrupt mapping for more details. 4. before servicing an interrupt, the cc register is pus hed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. 5. if the pll is enabled by option byte, it outputs the clock after a delay of t startup (see figure 12: pll output frequency timing diagram ). 9.4.1 halt mode recommendations make sure that an external event is available to wake up the microcontroller from halt mode. when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as ?input pull-up with interrupt? before executing the halt reset interrupt (3) y n n y cpu oscillator peripherals (2) ibit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off x 4) on cpu oscillator peripherals ibit on on x 4) on 256 or 4096 cpu clock delay (5) watchdog enable disable wdghalt (1) 0 watchdog reset 1 cycle halt instruction (active-halt disabled) (awucsr.awuen=0)
st7lite20f2 ST7LITE25F2 st7lite29f2 power saving modes doc id 8349 rev 5 57/166 instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. for the same reason, reinitialize the level sens itiveness of each external interrupt as a precautionary measure. the opcode for the halt instruction is 0x8e . to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memory. for example, avoid defi ning a constant in program memory with the value 0x8e. as the halt instruction clears the interrupt ma sk in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 9.5 active-halt mode active-halt mode is the lowest power consumption mode of the mcu with a real time clock available. it is entered by executing the ?halt? instruction. the decision to enter either in activehalt or halt mode is given by the ltcsr/atcsr register status as shown in the following table: the mcu can exit active-halt mode on reception of a specific interrupt (see ta b l e 1 2 : interrupt mapping ) or a reset: when exiting active-halt mode by means of a reset, a 256 or 4096 cpu cycle delay occurs. after the start up delay, the cpu resumes operation by fetching the reset vector which woke it up (see figure 27: active-halt mode flow-chart ). when exiting active-halt mode by means of an interrupt, the cpu immediately resumes operation by servicing the inte rrupt vector which woke it up (see figure 27: active-halt mode flow-chart ). when entering active-halt mode, the i bit in the cc register is cleared to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, only the main oscillato r and the selected time r counter (lt/at) are running to keep a wake-up time base. all ot her peripherals are not clocked except those which get their clock supply from another cloc k generator (such as external or auxiliary oscillator). table 18. active-halt mode ltcsr1 tb1ie bit atcsr ovfie bit atcsrck1 bit atcsrck0 bit meaning 0xx0 active-halt mode disabled 00xx 1xxx active-halt mode enabled x101
power saving modes st7lite20f2 ST7LITE25F2 st7lite29f2 58/166 doc id 8349 rev 5 note: as soon as active-halt is enabled, executing a halt instruction while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. figure 26. active-halt timing overview 1. this delay occurs only if the mcu exits active-halt mode by means of a reset. figure 27. active-halt mode flow-chart 1. peripherals clocked with an external clock source can still be active. 2. only the rtc1 interrupt and some specific interrupt s can exit the mcu from active-halt mode. refer to table 12: interrupt mapping for more details. 3. before servicing an interrupt, the cc register is pus hed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. halt run run 256 or 4096 cpu cycle delay (1) reset or interrupt halt instruction fetch vector active- [active-halt enabled] halt instruction reset interrupt (2) y n n y cpu oscillator peripherals (1) ibit on off 0 off fetch reset vector or service interrupt cpu oscillator peripherals (1) ibit on off x (3) on cpu oscillator peripherals ibit on on x (3) on 256 or 4096 cpu clock delay (active-halt enabled) (awucsr.awuen=0) cycle
st7lite20f2 ST7LITE25F2 st7lite29f2 power saving modes doc id 8349 rev 5 59/166 9.6 auto-wakeup from halt mode auto wake up from halt (awuf) mode is similar to halt mode with the addition of a specific internal rc oscillator for wake-up (auto wake up from halt osc illator). compared to active-halt mode, awuf has lower power consumption (the main clock is not kept running, but there is no accurate realtime clock available. it is entered by executing the halt instruction when the awuen bit in the awucsr register has been set. figure 28. awuf mode block diagram as soon as halt mode is entered, and if the awuen bit has been set in the awucsr register, the awu rc oscillator provides a clock signal (f awu_rc ). its frequency is divided by a fixed divider and a programmable prescaler controlled by the awupr register. the output of this prescaler provides the delay time. when the delay has elapsed the awuf flag is set by hardware and an interrupt wakes-up the mcu from halt mode. at the same time the main oscillator is immediately turned on and a 256 or 4096 cycle delay is used to stabilize it. after this start-up delay, the cpu resumes operation by servicing the awuf interrupt. the awu flag and its associated interrupt are cleared by software reading the awucsr register. to compensate for any frequency dispersion of the awu rc oscillator, it can be calibrated by measuring the clock frequency f awu_rc and then calculating the right prescaler value. measurement mode is enabled by setting the awum bit in the awucsr register in run mode. this connects f awu_rc to the input capture of the 12-bit auto-reload timer, allowing the f awu_rc to be measured using the main oscillator clock as a reference timebase. similarities with halt mode: the following awuf mode behavior is the same as normal halt mode: the mcu can exit awuf mode by means of an y interrupt with exit from halt capability or a reset (see section 9.4: halt mode ). when entering awuf mode, the i bit in the cc register is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in awuf mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. none of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the awu oscillator). the compatibility of watchdog operation with awuf mode is configured by the wdghalt option bit in the option byte. depending on this setting, the halt instruction when executed while the watchdog system is enabled, can generate a watchdog reset. awu rc awufh f awu_rc (ei0 source) oscillator prescaler/1 .. 255 awufh interrupt /64 divider to timer input capture
power saving modes st7lite20f2 ST7LITE25F2 st7lite29f2 60/166 doc id 8349 rev 5 figure 29. awuf halt timing diagram figure 30. awuf mode flowchart 1. wdghalt is an option bit (see section 15.1: option bytes for more details). 2. peripheral clocked with an external clock source can still be active. 3. only an awuf interrupt and some specific interrupts can exit the mcu from halt mode (such as external awuf interrupt f cpu run mode halt mode 256 or 4096 t cpu run mode f awu_rc clear by software t awu reset interrupt (3) y n n y cpu main osc peripherals (2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu main osc peripherals i[1:0] bits on off xx (4) on cpu main osc peripherals i[1:0] bits on on xx (4) on 256 or 4096 cpu clock delay (5) watchdog enable disable wdghalt (1) 0 watchdog reset 1 cycle awu rc osc on awu rc osc off awu rc osc off halt instruction (active-halt disabled) (awucsr.awuen=1)
st7lite20f2 ST7LITE25F2 st7lite29f2 power saving modes doc id 8349 rev 5 61/166 interrupt). refer to table 12: interrupt mapping for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and recovered when the cc register is popped. 5. if the pll is enabled by option byte, it out puts the clock after an additional delay of t startup (see figure 12: pll output frequency timing diagram ). 9.6.1 register description awuf control/status register (cr) read/write reset value: 0000 0000 (0ch) bits 7:3 = reserved bit 2 = awuf auto-wakeup flag this bit is set by hardware when the awu module generates an interrupt and cleared by software on reading awucsr. writing to this bit does not change its value. 0: no awu interrupt occurred 1: awu interrupt occurred bit 1= awum auto-wakeup measurement this bit enables the awu rc oscillator and co nnects its output to the input capture of the 12-bit auto-reload timer. this allows the timer to be used to measure the awu rc oscillator dispersion and then compensate this dispersion by providing the right value in the awupre register. 0: measurement disabled 1: measurement enabled bit 0 = awuen auto wake up from halt enabled this bit enables the auto wake up from halt feature: once halt mode is entered, the awuf wakes up the microcontroller after a time delay dependent on the awu prescaler value. it is set and cleared by software. 0: awuf (auto wake up from halt) mode disabled 1: awuf (auto wake up from halt) mode enabled 7 0 00000awufawumawuen
power saving modes st7lite20f2 ST7LITE25F2 st7lite29f2 62/166 doc id 8349 rev 5 awuf prescaler register list (awupr) read/write reset value: 1111 1111 (ffh) bits 7:0= awupr[7:0] auto-wakeup prescaler these 8 bits define the awupr dividing factor (as explained in ta b l e 1 9 : aw u prescaler below): in awu mode, the period that the mcu stays in halt mode (t awu in figure 29: awuf halt timing diagram ) is defined by: this prescaler register can be programmed to modify the time that the mcu stays in halt mode before waking up automatically. note: if 00h is written to awupr, depending on th e product, an interrupt is generated immediately after a halt instruction, or the awupr remains unchanged. bit 7 ?????? 0 value awupr7 awupr6 awupr5 awupr4 awupr3 awupr2 awupr1 awupr0 table 19. awu prescaler awupr[7:0 ] dividing factor 00h forbidden 01h 1 ?? feh 254 ffh 255 t awu 64 awupr 1 f awurc -------------------- t rcstrt + = table 20. awu register map and reset values address (hex.) register label 76543210 0049h awupr reset value awupr 1 awupr 1 awupr 1 awupr 1 awupr 1 awupr 1 awupr 1 awupr 1 004ah awucsr reset value 0 0 0 0 0 awuf awum awuen
st7lite20f2 ST7LITE25F2 st7lite29f2 i/o ports doc id 8349 rev 5 63/166 10 i/o ports 10.1 introduction the i/o ports allow data transfer. an i/o port can contain up to 8 pins. each pin can be programmed independently either as a digital input or digital output. in addition, specific pins may have several other functions. these functions can include external interrupt, alternate signal input/output for on chip peripherals or analog input. 10.2 functional description a data register (dr) and a data direction register (ddr) are always associated with each port. the option register (or), which allows input/output options, may or may not be implemented. the following description takes into account the or register. refer to section 10.7: device-specific i/o port configuration for device specific information. an i/o pin is programmed using the corresponding bits in the ddr, dr and or registers: bit x corresponding to pin x of the port. figure 31 shows the generic i/o block diagram. 10.2.1 input modes clearing the ddrx bit selects input mode. in this mode, reading its dr bit returns the digital value from that i/o pin. if an or bit is available, different input modes can be configured by software: floating or pull- up. refer to i/o port implementation section for configuration. note: writing to the dr modifies the latch value but does not change the state of the input pin. do not use read/modif y/write instructions (bset/bres) to modify the dr register. external interrupt function depending on the device, setting the orx bit while in input mode can configure an i/o as an input with interrupt. in this configuration, a signal edge or level input on the i/o generates an interrupt request via the corresponding interrupt vector (eix). falling or rising edge sensitivity is programmed independently for each interrupt vector. the external interrupt control register (eicr) or the miscellaneous register controls this sensitivity, depending on the device. each external interrupt vector is linked to a dedicated group of i/o port pins (see pinout description in section 2: pin description and section : interrupts . if several i/o interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. for this reason if one of the interrupt pins is tied low, it may mask the others. external interrupts are hardware interrupts. fetching the corresponding interrupt vector automatically clears the request latch. changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts.
i/o ports st7lite20f2 st 7lite25f2 st7lite29f2 64/166 doc id 8349 rev 5 spurious interrupts when enabling/disabling an external interrupt by setting/resetting the related or register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. this is due to the edge dete ctor input which is s witched to '1' when the external interrupt is disabled by the or register. to avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the or register bit and configuring the appropriate sensitivity again. caution: in case a pin level change occurs during these operations (asynchronous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge. this corresponds to the following steps: 1. to enable an external interrupt: ? set the interrupt mask with the sim instruction (in cases where a pin level change could occur) ? select rising edge ? enable the external interrupt through the or register ? select the desired sensitivity if different from rising edge ? reset the interrupt mask with the rim instruction (in cases where a pin level change could occur). 2. to disable an external interrupt: ? set the interrupt mask with the sim instruction sim (in cases where a pin level change could occur) ? select falling edge ? disable the external interrupt through the or register ? select rising edge ? reset the interrupt mask with the rim instruction (in cases where a pin level change could occur). 10.2.2 output modes setting the ddrx bit selects output mode. writing to the dr bits applies a digital value to the i/o through the latch. reading the dr bits returns the previously stored value. if an or bit is available, different output modes can be selected by software: push-pull or opendrain. refer to i/o port implementation section for configuration. table 21. dr value and output pin status dr push-pull open-drain 0v ol v ol 1v oh floating
st7lite20f2 ST7LITE25F2 st7lite29f2 i/o ports doc id 8349 rev 5 65/166 10.2.3 alternate functions many st7s i/os have one or more alternate functions. these may include output signals from, or input signals to, on-chip peripherals. the device pin description table describes which peripheral signals can be input/output to which ports. a signal coming from an on-chip peripheral can be output on an i/o. to do this, enable the on-chip peripheral as an output (enable bit in the peripheral?s control register). the peripheral configures the i/o as an output and takes priority over standard i/o programming. the i/o?s state is readable by addressing the corresponding i/o data register. configuring an i/o as floating enables alternate function input. it is not recommended to configure an i/o as pull-up as th is will increase current consumption. before using an i/o as an alternate input, configure it without interrupt. otherwise spurious interrupts can occur. configure an i/o as input floating for an on-chip peripheral signal which can be input and output. caution: i/os which can be configured as both an analog and digital alternate function need special attention. the user must control the peripherals so that the signals do not arrive at the same time on the same pin. if an external clock is used, only the clock alternate function should be employed on that i/o pin and not the other alternate function. figure 31. i/o port general block diagram dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external request (ei x ) interrupt sensitivity selection cmos schmitt trigger register access bit from on-chip periphera l to on-chip peripheral . combinational logic
i/o ports st7lite20f2 st 7lite25f2 st7lite29f2 66/166 doc id 8349 rev 5 note: refer to the section 10.7: device-specific i/o port configuration for device specific information. table 22. i/o port mode options (1) 1. legend: ni - not implemented off - implemented not activated on - implemented and activated. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (2) 2. the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ol is implemented to protect the device against positive stress. table 23. i/o configurations i/o port hardware configuration input (1) note 3 condition pad v dd r pu external interrupt polarity databus pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register condition alternate input analog input to on-chip peripheral combinational logic
st7lite20f2 ST7LITE25F2 st7lite29f2 i/o ports doc id 8349 rev 5 67/166 analog alternate function configure the i/o as floating input to use an adc input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the adc input. analog recommendations do not change the voltage level or loading on any i/o while conversion is in progress. do not have clocking pins located close to a selected analog pin. warning: the analog input voltage le vel must be within the limits stated in the absolute maximum ratings. 10.3 i/o port implementation the hardware implementation on each i/o port depends on the settings in the ddr and or registers and specific i/o port features such as adc input or open drain. switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommend ed safe transitions are illustrated in figure 32 . other transitions are potentially risky and s hould be avoided, since they may present unwanted side-effects such as spurious interrupt generation. open-drain output (2) push-pull output (3) 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read th e alternate function output status. 2. when the i/o port is in output configuration and t he associated alternate func tion is enabled as an input, the alternate function reads the pin stat us given by the dr register content. 3. for true open drain, these elements are not implemented. table 23. i/o configurations (continued) i/o port hardware configuration note 3 pad r pu databus dr dr register access r/w v dd register pad r pu databus dr dr register access r/w v dd alternate alternate enable output register bit from on-chip periphera l note 3
i/o ports st7lite20f2 st 7lite25f2 st7lite29f2 68/166 doc id 8349 rev 5 figure 32. interrupt i/o port state transitions 10.4 unused i/o pins unused i/o pins must be connected to fixed voltage levels. refer to section 13.8: i/o port pin characteristics . 10.5 low power modes 10.6 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and if the i bit in the cc register is cleared (rim instruction). 10.7 device-specific i/o port configuration the i/o port register configurations are summarized as follows: standard ports 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or table 24. effect of low power modes on i/o ports mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupt s cause the device to exit from halt mode. table 25. i/o port interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event ? ddrx orx ye s ye s table 26. ports pa7:0, pb6:0 mode ddr or floating input 0 0 pull-up input 0 1
st7lite20f2 ST7LITE25F2 st7lite29f2 i/o ports doc id 8349 rev 5 69/166 note: on ports where the external interrupt capability is selected using the eisr register, the configuration will be as follows: interrupt ports open drain output 1 0 push-pull output 1 1 table 27. port configuration (standard ports) port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:0 floating pull-up open drain push-pull port b pb6:0 floating pull-up open drain push-pull table 26. ports pa7:0, pb6:0 (continued) mode ddr or table 28. port configuration (interrupt ports) port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:0 floating pull-up interrupt open drain push-pull port b pb6:0 floating pull-up interrupt open drain push-pull table 29. ports where the external interrupt capability selected using the eisr register mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 table 30. i/o port register map and reset values address (hex.) register label 76543210 0000h padr reset value msb 1111111 lsb 1 0001h paddr reset value msb 0000000 lsb 0 0002h paor reset value msb 0100000 lsb 0
i/o ports st7lite20f2 st 7lite25f2 st7lite29f2 70/166 doc id 8349 rev 5 0003h pbdr reset value msb 1111111 lsb 1 0004h pbddr reset value msb 0000000 lsb 0 0005h pbor reset value msb 0000000 lsb 0 table 30. i/o port register map and reset values (continued) address (hex.) register label 76543210
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 71/166 11 on-chip peripherals 11.1 watchdog timer (wdg) 11.1.1 introduction the watchdog timer is used to detect the oc currence of a software fault, usually generated by external interference or by unforeseen lo gical conditions, which causes the application program to abandon its normal sequence. the watchdog circuit generates an mcu reset on expiry of a programmed time period, unless the program refreshes the counter?s contents before the t6 bit becomes cleared. 11.1.2 main features programmable free-running downcounter (64 increments of 16000 cpu cycles) programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte. 11.1.3 functional description the counter value stored in the cr register (bits t[6:0]), is decremented every 16000 machine cycles, and the length of the time-out period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 become s cleared), it initiates a rese t cycle pulling low the reset pin for typically 30 s. figure 33. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 16000 t1 t2 t3 t4 t5
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 72/166 doc id 8349 rev 5 the application program must write in the cr register at regular intervals during normal operation to prevent an mcu reset. this downcounter is freerunning: it counts down even if the watchdog is disabled. the value to be stored in the cr register must be between ffh and c0h (see table 31: watchdog timing ): ? the wdga bit is set (watchdog enabled) ? the t6 bit is set to prevent generating an immediate reset ? the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. note: the number of cpu clock cycles applied during the reset phase (256 or 4096) must be taken into account in addition to these timings. 11.1.4 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the option byte description in section 15: device configuration . using halt mode or active-halt mode with the wdg (wdghalt option) if halt mode with watchdog is enabled by option byte (no watchdog reset on halt instruction), it is recommended before executing the halt instruction to refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcontroller. same behavior in active-halt mode. 11.1.5 interrupts none. table 31. watchdog timing (1) 1. the timing variation is due to the unknown status of the prescaler when writing to the cr register. f cpu = 8 mhz wdg counter code min [ms] max [ms] c0h 1 2 ffh 127 128
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 73/166 11.1.6 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watchdog option is enabled by option byte. bits 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). 11.2 12-bit autoreload timer 2 (at2) 11.2.1 introduction the 12-bit autoreload timer can be used for gen eral-purpose timing functions. it is based on a free-running 12-bit upcounter with an input capture register and four pwm output channels. there are 6 external pins: ? four pwm outputs ? atic pin for the input capture function ? break pin for forcing a break condition on th e pwm outputs. 7 0 wdga t6 t5 t4 t3 t2 t1 t0 table 32. watchdog timer register map and reset values address (hex.) register label 76543210 002eh wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 74/166 doc id 8349 rev 5 11.2.2 main features 12-bit upcounter with 12-bit autoreload register (atr) maskable overflow interrupt generation of four independent pwmx signals frequency 2 khz-4 mhz (@ 8 mhz f cpu ) ? programmable duty-cycles ? polarity control ? programmable output modes ? maskable compare interrupt input capture ? 12-bit input capture register (aticr) ? triggered by rising and falling edges ? maskable ic interrupt. figure 34. block diagram 11.2.3 functional description pwm mode this mode allows up to four pulse width modulated signals to be generated on the pwmx output pins. the pwmx output signals can be enabled or disabled using the oex bits in the pwmcr register. atcsr cmpie ovfie ovf ck0 ck1 icie icf 0 12-bit autoreload register 12-bit upcounter cmpf2 cmpf1 cmpf3 cmpf0 cmp request ovf interrupt request f cpu atic 12-bit input capture register ic interrupt request atr aticr f counter cntr 32 mhz (1 ms f ltimer @ 8mhz) cmpfx bit pwm generation polarity opx bit pwmx comp- pare f pwm output control oex bit 4 pwm channels interrupt timebase dcr0h dcr0l preload preload on ovf event 12-bit duty cycle value (shadow) if tran=1
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 75/166 pwm frequency and duty cycle the four pwm signals have the same frequency (f pwm ) which is controlled by the counter period and the atr register value. f pwm = f counter / (4096 - atr) following the above formula, ?if f counter is 32 mhz, the maximum value of f pwm is 8 mhz (atr register value = 4092), the minimum value is 8 khz (atr register value = 0) ?if f counter is 4 mhz , the maximum value of f pwm is 2 mhz (atr register value = 4094),the minimum value is 1 khz (atr register value = 0). note: the maximum value of atr is 4094 because it must be lower than the dcr value which must be 4095 in this case. at reset, the counter starts counting from 0. when a upcounter overflow occurs (ovf ev ent), the preloaded duty cycle values are transferred to the duty cycle registers and the pwmx signals are set to a high level. when the upcounter matches the dcrx value the pwmx signals are set to a low level. to obtain a signal on a pwmx pin, the contents of the corresponding dcrx register must be greater than the contents of the atr register. the polarity bits can be used to invert any of the four output signals. the inversion is synchronized with the counter overflow if the tran bit in the trancr register is set (reset value). see figure 35 . figure 35. pwm inversion diagram the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (4096 ? atr) note: to get the maximum resolution (1/4096), the atr register must be 0. with this maximum resolution, 0% and 100% can be obtained by changing the polarity. pwmx pwmx pin counter overflow opx pwmxcsr register inverter dff tran trancr register
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 76/166 doc id 8349 rev 5 figure 36. pwm function figure 37. pwm signal from 0% to 100% duty cycle output compare mode to use this function, load a 12-bit value in the dcrxh and dcrxl registers. when the 12-bit upcounter (cntr) reaches the value stored in the dcrxh and dcrxl registers, the cmpf bit in the pwmxcsr register is set and an interrupt request is generated if the cmpie bit is set. note: the output compare function is only available for dcrx values other than 0 (reset value). break function the break function is used to perform an emergency shutdown of the power converter. the break function is activated by the external break pin (active low). in order to use the break pin it must be previously enabled by software setting the bpen bit in the breakcr register. when a low level is detected on the break pin, the ba bit is set and the break function is activated. duty cycle register auto-reload register pwmx output t 4095 000 with oe=1 and opx=0 (atr) (dcrx) with oe=1 and opx=1 counter counter pwmx output t with oex=1 and opx=0 ffdh ffeh fffh ffdh ffeh fffh ffdh ffeh dcrx=000h dcrx=ffdh dcrx=ffeh dcrx=000h atr= ffdh f counter pwmx output with oex=1 and opx=1
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 77/166 software can set the ba bit to activate th e break functi on without using the break pin. when the break function is activated (ba bit =1): ? the break pattern (pwm[3:0] bits in the breakcr) is forced directly on the pwmx output pins (after the inverter), ? the 12-bit pwm counter is set to its reset value, ? the arr, dcrx and the corresponding sh adow registers are set to their reset values, ? the pwmcr register is reset. when the break function is deactivated after applying the break (ba bit goes from 1 to 0 by software): ? the control of pwm outputs is transferred to the port registers. figure 38. block diagram of break function note: the break pin value is latched by the ba bit. input capture the 12-bit aticr register is used to latch the value of the 12-bit free running upcounter after a rising or falling edge is detected on the atic pin. when an input capture occurs, the icf bit is set and the aticr register contains the value of the free running upcounter. an ic interrupt is gene rated if the icie bit is set. the icf bit is reset by reading the aticr register when the icf bit is set. the aticr is a read only register and always contains the free running upcounter value which corresponds to the most recent input capture. any further input capture is inhibited while the icf bit is set. pwm0 pwm1 pwm2 pwm3 1 0 pwm0 pwm1 pwm2 pwm3 breakcr register break pin pwm counter -> reset value arr & dcrx -> reset value pwm mode -> reset value when ba is set: (active low) (inverters) pwm0 pwm1 pwm2 pwm3 bpen ba
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 78/166 doc id 8349 rev 5 figure 39. input capture timing diagram 11.2.4 low power modes 11.2.5 interrupts counter t 01h f counter xxh 02h 03h 04h 05h 06h 07h 04h atic pin icf flag icr register interrupt 08h 09h 0ah interrupt aticr read 09h table 33. effect of low power modes mode description slow the input frequency is divided by 32 wait no effect on at timer active-halt at timer halted except if ck0=1, ck1=0 and ovfie=1 halt at timer halted table 34. interrupts events interrupt event (1) 1. the cmp and ic events are connected to the same interrupt vector. the ovf event is mapped on a separate vector (see interrupts chap ter). they generate an interrupt if the enable bit is set in the atcsr register and the interrupt mask in the cc register is reset (rim instruction). event flag enable control bit exit from wait exit from halt exit from active-halt overflow event ovf ovie yes no yes (2) 2. only if ck0=1 and ck1=0 (f counter = f ltimer ) ic event icf icie yes no no cmp event cmpf0 cmpie yes no no
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 79/166 11.2.6 register description timer control status register (atcsr) read / write reset value: 0x00 0000 (x0h) bit 7 = reserved. bit 6 = icf input capture flag this bit is set by hardware and cleared by software by reading the aticr register (a read access to aticrh or aticrl will clear th is flag). writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred bit 5 = icie ic interrupt enable this bit is set and cleared by software. 0: input capture interrupt disabled 1: input capture interrupt enabled bits 4:3 = ck[1:0] counter clock selection these bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. bit 2 = ovf overflow flag this bit is set by hardware and cleared by software by reading the tcsr register. it indicates the transition of the counter from fffh to atr value. 0: no counter overflow occurred 1: counter overflow occurred bit 1 = ovfie overflow interrupt enable this bit is read/write by software and cleared by hardware after a reset. 0: ovf interrupt disabled. 1: ovf interrupt enabled. bit 0 = cmpie compare interrupt enable this bit is read/write by software and cleared by hardware after a reset. it can be used 76 0 0 icf icie ck1 ck0 ovf ovfie cmpie table 35. counter clock selection counter clock selection ck1 ck0 off 0 0 f lt i m e r (1 ms timebase @ 8 mhz) (1) 1. pwm mode and output compare modes ar e not available at this frequency. 01 f cpu 10 32 mhz (2) 2. aticr counter may return inaccurate results when read. it is therefore not recommended to use input capture mode at this frequency. 11
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 80/166 doc id 8349 rev 5 to mask the interrupt generated when the cmpf bit is set. 0: cmpf interrupt disabled. 1: cmpf interrupt enabled. counter register high (cntrh) read only reset value: 0000 0000 (000h) counter register low (cntrl) read only reset value: 0000 0000 (000h) bits 15:12 = reserved bits 11:0 = cntr[11:0] counter value this 12-bit register is read by software and cleared by hardware after a reset. the counter is incremented continuously as soon as a counter clock is selected. to obtain the 12-bit value, software should read the counter value in two consecutive read operations, lsb first. when a counter overflow occurs, the counter restarts from the value specified in the atr register. autoreload register (atrh) read / write reset value: 0000 0000 (00h) bits 15:12 = reserved bits 11:0 = atr[11:0] counter value this 12-bit register is read by software and cleared by hardware after a reset. the counter is incremented continuously as soon as a counter clock is selected. to obtain the 12-bit value, software should read the counter value in two consecutive read operations, lsb first. when a counter overflow occurs, the counter restarts from the value specified in the atr register. 15 8 0 0 0 0 cntr11 cntr10 cntr9 cntr8 7 0 cntr7 cntr6 cntr5 cntr4 cntr3 cntr2 cntr1 cntr0 15 8 0 0 0 0 at r 1 1 at r 1 0 at r 9 at r 8
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 81/166 autoreload register (atrl) read / write reset value: 0000 0000 (00h) i pwm output control register (pwmcr) read/write reset value: 0000 0000 (00h) bits 7:0 = oe[3:0] pwmx output enable these bits are set and cleared by software and cleared by hardware after a reset. 0: pwm mode disabled. pwmx output alternate function disabled: i/o pin free for general purpose i/o after an overflow event. 1: pwm mode enabled pwmx control status register (pwmxcsr) read / write reset value: 0000 0000 (00h) bits 7:2 = reserved, must be kept cleared bit 1 = opx pwmx output polarity this bit is read/write by software and cleared by hardware after a reset. this bit selects the polarity of the pwm signal. 0: the pwm signal is not inverted 1: the pwm signal is inverted bit 0 = cmpfx pwmx compare flag this bit is set by hardware and cleared by software by reading the pwmxcsr register. it indicates that the upcounter value matches the dcrx register value. 0: upcounter value does not match dcr value. 1: upcounter value matches dcr value 7 0 at r 7 at r 6 at r 5 at r 4 at r 3 at r 2 at r 1 at r 0 7 0 0oe30oe20oe10oe0 7 6 0 000000opxoe0
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 82/166 doc id 8349 rev 5 break control register (breakcr) read/write reset value: 0000 0000 (00h) bits 7:6 = reserved. forced by hardware to 0. bit 5 = ba break active this bit is read/write by software, cleared by hardware after reset and set by hardware when the break pin is low. it activa tes/deactivates the break function. 0: break not active 1: break active bit 4 = bpen break pin enable this bit is read/write by software and cleared by hardware after reset. 0: break pin disabled 1: break pin enabled bits 3:0 = pwm[3:0] break pattern these bits are read/write by software and cleared by hardware after a reset. they are used to force the four pwmx output signals into a stable state when the break function is active. pwmx duty cycle register high (dcrxh) read / write reset value: 0000 0000 (00h) pwmx duty cycle register low (dcrxl) read / write reset value: 0000 0000 (00h) bits 15:12 = reserved bits 11:0 = dcr[11:0] pwmx duty cycle value this 12-bit value is written by software. it defines the duty cycle of the corresponding pwm output signal (see figure 36 ). in pwm mode (oex=1 in the pwmcr register) the dcr[11:0] bits define the duty cycle of the pwmx output signal (see figure 36 ). in output compare mode, they define the value to be compared with the 12-bit upcounter value. 7 0 0 0 ba bpen pwm3 pwm2 pwm1 pwm0 15 8 0 0 0 0 dcr11 dcr10 dcr9 dcr8 7 0 dcr7 dcr6 dcr5 dcr4 dcr3 dcr2 dcr1 dcr0
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 83/166 input capture register high (aticrh) read only reset value: 0000 0000 (00h) input capture register low (aticrl) read only reset value: 0000 0000 (00h) bits 15:12 = reserved. bits 11:0 = icr[11:0] input capture data . this is a 12-bit register which is readable by software and cleared by hardware after a reset. the aticr register contains captured the value of the 12-bit cntr register when a rising or falling edge occurs on the atic pin. capt ure will only be performed when the icf flag is cleared. transfer control register (trancr) read/write reset value: 0000 0001 (01h) bits 7:1 reserved. forced by hardware to 0. bit 0 = tran transfer enable this bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. it allows the value of the dcrx registers to be transferred to the dcrx shadow registers after the next overflow event. the opx bits are transferred to the shadow opx bits in the same way. 15 8 0 0 0 0 icr11 icr10 icr9 icr8 7 0 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 7 0 0000000tran
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 84/166 doc id 8349 rev 5 table 36. register map and reset values address (hex.) register label 7654 3 2 10 0d atcsr reset value 0 icf 0 icie 0 ck1 0 ck0 0 ovf 0 ovfie 0 cmpie 0 0e cntrh reset value 0000 cntr11 0 cntr10 0 cntr9 0 cntr8 0 0f cntrl reset value cntr7 0 cntr8 0 cntr7 0 cntr6 0 cntr3 0 cntr2 0 cntr1 0 cntr0 0 10 atrh reset value 0000 at r 1 1 0 at r 1 0 0 at r 9 0 at r 8 0 11 atrl reset value at r 7 0 at r 6 0 at r 5 0 at r 4 0 at r 3 0 at r 2 0 at r 1 0 at r 0 0 12 pwmcr reset value 0 oe3 0 0 oe2 0 0 oe1 0 0 oe0 0 13 pwm0csr reset value 0000 0 0 op0 0 cmpf0 0 14 pwm1csr reset value 0000 0 0 op1 0 cmpf1 0 15 pwm2csr reset value 0000 0 0 op2 0 cmpf2 0 16 pwm3csr reset value 0000 0 0 op3 0 cmpf3 0 17 dcr0h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 18 dcr0l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 19 dcr1h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1a dcr1l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1b dcr2h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1c dcr2l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1d dcr3h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1e dcr3l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1f aticrh reset value 0000 icr11 0 icr10 0 icr9 0 icr8 0
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 85/166 11.3 lite timer 2 (lt2) 11.3.1 introduction the lite timer can be used for general-purpose timing functions. it is based on two free- running 8-bit upcounters, an 8-bit input capture register. 11.3.2 main features real-time clock ? one 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 mhz f osc ) ? one 8-bit upcounter with autoreload and programmable timebase period from 4s to 1.024 ms in 4 s increments (@ 8 mhz f osc ) ? 2 maskable timebase interrupts. input capture ? 8-bit input capture register (lticr) ? maskable interrupt with wakeup from halt mode capability. 20 aticrl reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 21 trancr reset value 0000 0 0 0 tran 1 22 breakcr reset value 00 ba 0 bpen 0 pwm3 0 pwm2 0 pwm1 0 pwm0 0 table 36. register map and reset values (continued) address (hex.) register label 7654 3 2 10
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 86/166 doc id 8349 rev 5 figure 40. lite timer 2 block diagram 11.3.3 functional description timebase counter 1 the 8-bit value of counter 1 cannot be read or written by software. after an mcu reset, it starts incrementing from 0 at a frequency of f osc /32. an overflow event occurs when the counter rolls over from f9h to 00h. if f osc = 8 mhz, then the time period between two counter overflow events is 1 ms. this period can be doubled by setting the tb bit in the ltcsr1 register. when counter 1 overflows, the tb1f bit is set by hardware and an interrupt request is generated if the tb1ie bit is set. the tb1f bit is cleared by software reading the ltcsr1 register. input capture the 8-bit input capture register is used to latch the free-running upcounter (counter 1) 1 after a rising or falling edge is detected on the ltic pin. when an input capture occurs, the icf bit is set and the lticr1 register contains the msb of counter 1. an interrupt is generated if the icie bit is set. the icf bit is cleared by reading the lticr register. ltcsr1 8-bit timebase /2 8-bit f ltimer 8 ltic f osc /32 tb1f tb1ie tb icf icie lttb1 interrupt request ltic interrupt request lticr input capture register 1 0 1 or 2 ms timebase (@ 8mhz f osc ) to 12-bit at timer f ltimer ltcsr2 tb2f 0 tb2ie 0 lttb2 8-bit timebase 0 0 8-bit autoreload register 8 ltcntr ltarr counter 2 counter 1 0 0 interrupt request
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 87/166 the lticr is a read-only register and always contains the data from the last input capture. input capture is inhibited if the icf bit is set. timebase counter 2 counter 2 is an 8-bit autoreload upcounter. it can be read by accessing the ltcntr register. after an mcu reset, it increments at a frequency of f osc /32 starting from the value stored in the ltarr register. a counter overflow event occurs when the counter rolls over from ffh to the ltarr reload value. software can write a new value at anytime in the ltarr register, this value will be automatically loaded in the co unter when the next overflow occurs. when counter 2 overflows, the tb2f bit in the ltcsr2 register is set by hardware and an interrupt request is generated if the tb2ie bit is set. the tb2f bit is cleared by software reading the ltcsr2 register. figure 41. input capture timing diagram 11.3.4 low power modes 04h 8-bit counter 1 t 01h f osc /32 xxh 02h 03h 05h 06h 07h 04h ltic pin icf flag lticr register cleared 4s (@ 8mhz f osc ) f cpu by s/w 07h reading ltic register table 37. effect of low power modes on lite timer mode description slow no effect on lite timer (this peripheral is driven directly by f osc /32) wait no effect on lite timer active-halt no effect on lite timer halt lite timer stops counting
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 88/166 doc id 8349 rev 5 11.3.5 interrupts note: the tbxf and icf interrupt events are connected to separate interrupt vectors (see interrupts chapter). they generate an interrupt if the enable bit is set in the ltcsr1 or ltcsr2 register and the interrupt mask in the cc register is reset (rim instruction). 11.3.6 register description lite timer control/status register 2 (ltcsr2) read / write reset value: 0000 0000 (00h) bits 7:2 = reserved, must be kept cleared. bit 1 = tb2ie timebase 2 interrupt enable this bit is set and cleared by software. 0: timebase (tb2) interrupt disabled 1: timebase (tb2) interrupt enabled bit 0 = tb2f timebase 2 interrupt flag this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter 2 overflow 1: a counter 2 overflow has occurred. table 38. tbxf and icf interrupt events interrupt event event flag enable control bit exit from wait exit from active- halt exit from halt timebase 1 event tb1f tb1ie yes yes no timebase 2 event tb2f tb2ie yes no no ic event icf icie yes no no 7 0 000000tb2ietb2f
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 89/166 lite timer autoreload register (ltarr) read / write reset value: 0000 0000 (00h) bits 7:0 = ar[7:0] counter 2 reload value these bits register is read/write by software. the ltarr value is automatically loaded into counter 2 (ltcntr) wh en an overflow occurs. lite timer counter 2 (ltcntr) read only reset value: 0000 0000 (00h) bits 7:0 = cnt[7:0] counter 2 reload value this register is read by software. the ltarr value is automatically loaded into counter 2 (ltcntr) when an overflow occurs. lite timer control/status register (ltcsr1) read / write reset value: 0x00 0000 (x0h) bit 7 = icie interrupt enable this bit is set and cleared by software. 0: input capture (ic) interrupt disabled 1: input capture (ic) interrupt enabled bit 6 = icf input capture flag this bit is set by hardware and cleared by software by reading the lticr register. writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred note: after an mcu reset, software must initialise the icf bit by reading the lticr register bit 5 = tb timebase period selection this bit is set and cleared by software. 7 0 ar7 ar7 ar7 ar7 ar3 ar2 ar1 ar0 7 0 cnt7 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 7 0 icie icf tb tb1ie tb1f ???
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 90/166 doc id 8349 rev 5 0: timebase period = t osc * 8000 (1 ms @ 8 mhz) 1: timebase period = t osc * 16000 (2 ms @ 8 mhz) bit 4 = tb1ie timebase interrupt enable this bit is set and cleared by software. 0: timebase (tb1) interrupt disabled 1: timebase (tb1) interrupt enabled bit 3 = tb1f timebase interrupt flag this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter overflow 1: a counter overflow has occurred bit 2:0 = reserved. lite timer input capture register (lticr) read only reset value: 0000 0000 (00h) bits 7:0 = icr[7:0] input capture value these bits are read by software and cleared by hardware after a reset. if the icf bit in the ltcsr is cleared, the value of the 8-bi t up-counter will be captur ed when a rising or falling edge occurs on the ltic pin. 7 0 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 table 39. lite timer register map and reset values address (hex.) register label 76543210 08 ltcsr2 reset value 000000 tb2ie 0 tb2f 0 09 ltarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 0a ltcntr reset value cnt7 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 0b ltcsr1 reset value icie 0 icf x tb 0 tb1ie 0 tb1f 0 000 0c lticr reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 91/166 11.4 serial peripheral interface (spi) 11.4.1 introduction the serial peripheral interface (spi) allows full-duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.4.2 main features full duplex synchronous transfers (on 3 lines) simplex synchronous transfers (on 2 lines) master or slave operation six master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mo de fault and overrun flags. note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 11.4.3 general description figure 42 shows the serial peripheral interface (spi) block diagram. there are 3 registers: spi control register (spicr) spi control/status register (spicsr) spi data register (spidr) the spi is connected to external devices through 3 pins: miso: master in / slave out data mosi: master out / slave in data sck: serial clock out by spi masters and input by spi slaves ss : slave select: this input signal acts as a "chip select? to let the spi master communicate with slaves individually and to avoid contention on the data lines. slave ss inputs can be driven by standard i/o ports on the master device.
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 92/166 doc id 8349 rev 5 figure 42. serial peripheral interface block diagram functional description a basic example of interconnections between a single master and a single slave is illustrated in figure 43: single master/ single slave application . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is always initiated by th e master. when the master device transmits data to a slave device via mosi pin, the sl ave device responds by sending data to the master device via the miso pin. this implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node (in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 46: data clock timing diagram ) but master and slave must be programmed with the same timing mode. spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 93/166 figure 43. single master/ single slave application slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr register (see figure 45: hardware/software slave select management ). in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: s s internal must be held high continuously. in slave mode : there are two cases depending on the data/clock timing relationship (see figure 44 ): 1. if cpha=1 (data latched on 2nd clock edge): s s internal must be held low during the entire transmission. this im plies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by managing the ss function by software (ssm= 1 and ssi=0 in the spicsr register), 2. if cpha=0 (data latched on 1st clock edge): s s internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. if ss is not pulled high, a write collision error will occu r when the slave writes to the shift register (see write collision error (wcol) ). figure 44. generic ss timing diagram 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software byte 1 byte 2 byte 3 mosi/miso master s s slave s s (if cpha=0) slave ss (if cpha=1)
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 94/166 doc id 8349 rev 5 figure 45. hardware/software slave select management master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). how to operate the spi in master mode to operate the spi in master mode, perform the following steps in order (if the spicsr register is not written first, the spicr register setting (mstr bit) may be not taken into account): 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 46 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits. note: mstr and spe bits re main set only if ss is high. if the spicsr register is not written first, the spicr register setting (mstr bit) may be not taken into account. the transmit sequence begins when software writes a byte in the spidr register. master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: 1. the spif bit is set by hardware. 2. an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register. 1 0 ss i nternal ssm bit ssi bit ss external pin
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 95/166 note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the following actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 46: data clock timing diagram ). note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in slave select management and figure 44: generic ss timing diagram . if cpha=1 ss must be held low continuously. if cpha=0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and se t the spe bit to enable the spi i/o functions. slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware. ? an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set. 2. a write or a read to the spidr register. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section : overrun condition (ovr) ). 11.4.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 46: data clock timing diagram ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge.
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 96/166 doc id 8349 rev 5 figure 46 shows an spi transfer with the four combinations of the cpha and cpol bits. the diagram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit. figure 46. data clock timing diagram note: this figure should not be used as a replacement for parametric information. refer to the section 13: electrical characteristics . 11.4.5 error flags master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: 1. the modf bit is set and an spi interrupt request is generated if the spie bit is set. 2. the spe bit is reset. this blocks all output from the device and disables the spi peripheral. 3. the mstr bit is reset, thus forcing the device into slave mode. sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 msbit bit 6 bit 5 bit 4 bit3bit 2bit 1lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0)
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 97/166 clearing the modf bit is done through a software sequence: 1. a read access to the spicsr regi ster while the modf bit is set. 2. a write to the spicr register. note: to avoid any conflicts in an ap plication with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their original state during or after this clearing sequence. hardware does not allow the us er to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multi master configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset or return to an application default state. overrun condition (ovr) an overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: ? the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. write collision error (wcol) a write collision occurs when the software trie s to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted; and the softwa re write will be unsuccessful. write collisions can occur both in master and slave mode. see also section : slave select management . note: a "read collision" will never occu r since the received data byte is placed in a buffer in which access is always synchronous with the cpu operation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 47: clearing the wcol bit (write collision flag) software sequence ).
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 98/166 doc id 8349 rev 5 figure 47. clearing the wcol bit (write collision flag) software sequence 1. writing to the spidr register instead of reading it does not reset the wcol bit single master and multimaster configurations there are two types of spi systems: 1. single master system 2. multimaster system. single master system a typical single master system may be configured, using a device as the master and four devices as slaves (see figure 48 ). the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are connected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with command fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be implemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the spicr register and the modf bit in the spicsr register. clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif =0 wcol=0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 read spicsr read spidr result result
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 99/166 figure 48. single master / multiple slave configuration 11.4.6 low power modes using the spi to wake up the device from halt mode in slave configuration, the spi is able to wake up the device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to perform an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the device from halt mode only if the slave select signal (external ss pin or the ssi bit in the spi csr register) is low when the device enters halt mode. so if slave selection is configured as external (see section : slave select management ), make sure the master drives a low level on the ss pin when the slave enters halt mode. miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave device slave device slave device slave device master device table 40. wait and halt mode description mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the device is woken up by an interrupt with ?exit from halt mode? capability. the data received is subsequently read from th e spidr register when the software is running (interrupt vector fetching). if several data are received before the wakeup event, then an overrun error is generated. this error can be detected after the fetch of the interrupt r outine that woke up the device.
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 100/166 doc id 8349 rev 5 11.4.7 interrupts note: the spi interrupt events are connected to the same interrupt vector (see section 8: interrupts ). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 11.4.8 register description control register (spicr) read/write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever an end of transfer event, master mode fault or overrun error occurs (spif=1, modf=1 or ovr=1 in the spicsr register). bit 6 = spe serial peripheral output enable this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section : master mode fault (modf) ). the spe bit is cleared by reset, so the spi peripheral is not initially connected to the external pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled. bit 5 = spr2 divider enable this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 42: spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4 = mstr master mode this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section : master mode fault (modf) ). 0: slave mode table 41. interrupt events interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie ye s ye s master mode fault event modf yes no overrun error ovr yes no 7 0 spie spe spr2 mstr cpol cpha spr1 spr0
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 101/166 1: master mode. the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity this bit is set and cleared by software. this bit determines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit. bit 2 = cpha clock phase this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. control/status register (spicsr) read/write (some bits are read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only) this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an external device has been completed. table 42. spi master mode sck frequency serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 7 0 spif wcol ovr modf - sod ssm ssi
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 102/166 doc id 8349 rev 5 note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. bit 6 = wcol write collision status (read only) this bit is set by hardware when a write to the spidr register is done during a transmit sequence. it is cleared by a software sequence (see figure 47: clearing the wcol bit (write collision flag) software sequence ). 0: no write collision occurred 1: a write collision has been detected. bit 5 = ovr s pi overrun error (read only) this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section : overrun condition (ovr) ). an interrupt is generated if sp ie = 1 in the spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section : master mode fault (modf) ). an spi interrupt can be generated if spie=1 in the spicr register. this bit is cleared by a software sequence (an access to the spicsr register while modf=1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode). 0: spi output enabled (if spe=1) 1: spi output disabled. bit 1 = ssm ss management. this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section : slave select management . 0: hardware management (ss managed by external pin) 1: software management (internal ss signal controlled by ssi bit. external ss pin free for general-purpose i/o). bit 0 = ssi ss internal mode. this bit is set and cleared by software. it ac ts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0: slave selected 1: slave deselected.
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 103/166 data i/o register (spidr) read/write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this regi ster will initiate transmission/ reception of another byte. note: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. caution: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value located in the buffer and not the content of the shift register (see figure 42: serial peripheral interface block diagram ). 11.5 10-bit a/d converter (adc) 11.5.1 introduction the analog to digital converter (adc) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. this peripheral has up to 7 multiplexed analog input channels (refer to table 2: device pin description ) that allow the peripheral to convert the analog voltage levels from up to 7 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 7 0 d7 d6 d5 d4 d3 d2 d1 d0 table 43. spi register map and reset values address (hex.) register label 76543210 0031h spidr reset value msb xxxxxxx lsb x 0032h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0033h spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 104/166 doc id 8349 rev 5 11.5.2 main features 10-bit conversion up to 7 channels with multiplexed input linear successive approximation data register (dr) whic h contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 49 . 11.5.3 functional description analog power supply v dda and v ssa are the high and low level reference voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. figure 49. adc block diagram input voltage amplifier the input voltage can be amplified by a factor of 8 by enabling the am psel bit in the adcdrl register. when the amplifier is enabled, the input range is 0 v to v dd /8. ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 3 d1 d0 adcdrl 00 0 amp slow amp 0 r adc c adc hold control x 1 or x 8 ampsel bit sel f adc f cpu 0 1 1 0 div 2 div 4 slow bit cal
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 105/166 for example, if v dd = 5 v, then the adc can convert voltages in the range 0 v to 430 mv with an ideal resolution of 0.6 mv (equivalent to 13-bit resolution with reference to a v ss to v dd range). note: for more details, refer to section 13: electrical characteristics . the amplifier is switched on by the adon bi t in the adccsr register, so no additional startup time is required when the amp lifier is selected by the ampsel bit. digital a/d conversion result the conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v dda (high-level voltage reference) then the conversion result is ffh in the adcdrh register and 03h in the adcdrl register (without overflow indication). if the input voltage (v ain ) is lower than v ssa (low-level voltage reference) then the conversion result in the adcdrh and adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conv ersion is stored in the adcdrh and adcdrl registers. the accuracy of the conversion is described in section 13: electrical characteristics . r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and samp ling not being completed in the allowed time. a/d conversion the analog input ports must be configured as input, no pull-up, no interrupt. section 10: i/o ports . using these pins as analog inputs does not affect the abilit y of the port to be read as a logic input. in the adccsr register, select the cs[2:0] bits to assign the analog channel to convert. adc conversion mode in the adccsr register: ? set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: ? the eoc bit is set by hardware. ? the result is in the adcdr registers. a read to the adcdrh resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll eoc bit 2. read adcdrl 3. read adcdrh. this cl ears eoc automatically. to read only 8 bits, perform the following steps: 1. poll eoc bit 2. read adcdrh. this cl ears eoc automatically.
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 106/166 doc id 8349 rev 5 11.5.4 low power modes note: the a/d converter may be disabled by resetting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. 11.5.5 interrupts none. 11.5.6 register description control/status register (adccsr) read/write (except bit 7 read only) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleare d by software reading the adcdrh register. 0: conversion is not complete 1: conversion complete. bit 6 = speed adc clock selection this bit is set and cleared by software. it is used together with the slow bit to configure the adc clock speed. refer to the table in the slow bit description. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter and amplifier are switched off 1: a/d converter and amplifier are switched on. bits 4:3 = reserved. must be kept cleared. bits 2:0 = ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. table 44. low power modes effects mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time t stab (see electrical characteristics) before accurate conversions can be performed. 7 0 eoc speed adon 0 ch3 ch2 ch1 ch0 table 45. channel selection bits channel pin (1) ch2 ch1 ch0 ain0 000 ain1 001
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 107/166 ain2 010 ain3 011 ain4 100 ain5 101 ain6 110 1. the number of channels is device dependent. refer to table 2: device pin description . table 45. channel selection bits (continued) channel pin (1) ch2 ch1 ch0
on-chip peripherals st7lite20f 2 ST7LITE25F2 st7lite29f2 108/166 doc id 8349 rev 5 data register high (adcdrh) read only reset value: xxxx xxxx (xxh) bits 7:0 = d[9:2] msb of analog converted value. amp control/data register low (adcdrl) read/write reset value: 0000 00xx (0xh) bits 7:5 = reserved. forced by hardware to 0. bit 4 = ampcal amplifier calibration bit this bit is set and cleared by software. user is suggested to use this bit to calibrate the adc when amplifier is on. setting this bit internally connects am plifier input to 0v. hence, corresponding adc output can be used in software to eliminate amplifier-offset error. 0: calibration off 1: calibration on (the input voltage of the amp is set to 0v). note: it is advised to use this bit to calibrate the adc when the amplifier is on. setting this bit internally connects the amplifier input to 0v. hence, the corresponding adc output can be used in software to eliminate an amplifier-offset error. bit 3 = slow slow mode this bit is set and cleared by software. it is used together wit h the speed bit to configure the adc clock speed as shown ta bl e 4 6 . this bit is set and cleared by software. bit 2 = ampsel amplifier selection bit 0: amplifier is not selected 1: amplifier is selected bits 1:0 = d[1:0] lsb of analog converted value note: when ampsel=1 it is mandatory that f adc be less than or equal to 2 mhz. 7 0 d9 d8 d7 d6 d5 d4 d3 d2 7 0 0 0 0 amp cal slow ampsel d1 d0 table 46. adc clock speed selection f adc slow speed f cpu /2 0 0 f cpu 01 f cpu /4 1 x
st7lite20f2 ST7LITE25F2 st7lite29f2 on-chip peripherals doc id 8349 rev 5 109/166 table 47. adc register map and reset values address (hex.) register label 765 4 3210 0034h adccsr reset value eoc 0 speed 0 adon 0 0 0 0 0 ch2 0 ch1 0 ch0 0 0035h adcdrh reset value d9 x d8 x d7 x d6 x d5 x d4 x d3 x d2 x 0036h adcdrl reset value 0 0 0 0 0 0 ampcal 0 slow 0 ampsel 0 d1 x d0 x
instruction set st7lite20f2 ST7LITE25F2 st7lite29f2 110/166 doc id 8349 rev 5 12 instruction set 12.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in seven main groups: : the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdivided in two submodes called long and short: long addressing mode is more powerful because it can use the full 64 kbyte address space, however it uses more bytes and more cpu cycles. short addressing mode is less powerful because it can generally only access page zero (0000h00ffh range), but the instruction size is more compact, and faster. all memory to memory instructions use shor t addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap). the st7 assembler optimizes the use of long and short addressing modes. table 48. addressing mode groups addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 table 49. st7 addressing mode overview mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent ?? nop ??? + 0 immediate ?? ld a,#$55 ??? + 1 short direct ? ld a,$10 00..ff ?? + 1 long direct ? ld a,$1000 0000..ffff ?? + 2 no offset direct indexed ld a,(x) 00..ff ?? + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe ?? + 1 long direct indexed ld a,($1000,x) 0000..ffff ?? + 2 short indirect ? ld a,[$10] 00..ff 00..ff byte + 2 long indirect ? ld a,[$10.w] 0000..f fff 00..ff word + 2
st7lite20f2 ST7LITE25F2 st 7lite29f2 instruction set doc id 8349 rev 5 111/166 12.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required information for the cpu to process the operation. short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w ],x) 0000..ffff 00..ff word + 2 relative direct ? jrne loop pc-128/ pc+127 (1) ?? + 1 relative indirect ? jrne [$10] pc-128/ pc+127 (1) 00..ff byte + 2 bit direct ? bset $10,#7 00..ff ?? + 1 bit indirect ? bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff ?? + 2 bit indirect relative btjt [$10 ],#7,skip 00..ff 00..ff byte + 3 1. at the time the instruction is executed, the program counter (pc) points to the instruction following jrxx. table 49. st7 addressing mode overview (continued) table 50. inherent instructions instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication
instruction set st7lite20f2 ST7LITE25F2 st7lite29f2 112/166 doc id 8349 rev 5 12.1.2 immediate immediate instructions have two bytes: the first byte contains the opcode and the second byte contains the operand value. . 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two submodes: direct (short) the address is a byte, thus requiring only one byte after the opcode, but only allows 00 - ff addressing space. direct (long) the address is a word, thus allowing 64 kbyte addressing space, but requires 2 bytes after the opcode. 12.1.4 indexed (no of fset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indexed addressing mode consists of three submodes: indexed (no offset) there is no offset, (no extra byte after the opcode), and it allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requiring only one byte after the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte addressing space and requires 2 bytes after the opcode. sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles table 50. inherent instructions (continued) instruction function table 51. immediate instructions instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
st7lite20f2 ST7LITE25F2 st 7lite29f2 instruction set doc id 8349 rev 5 113/166 12.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (pointer). the pointer address follows the opcode. the indirect addressing mode consists of two submodes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. 12.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (x or y) with a pointer value located in memory. the pointer address follows the opcode. the indirect indexed addressing mode consists of two submodes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. i i table 52. long and short instructions supporting direct, indexed, indirect and indirect indexed addressing modes long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/subtractions operations bcp bit compare table 53. short instructions supporting di rect, indexed, indirect and indirect indexed addressing modes short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations
instruction set st7lite20f2 ST7LITE25F2 st7lite29f2 114/166 doc id 8349 rev 5 12.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. . the relative addressing mode consists of two submodes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in the memory, the address of which follows the opcode. 12.2 instruction groups the st7 family devices use an instruction set co nsisting of 63 instruct ions. the instructions may be subdivided into 13 ma in groups as illustrated in ta b l e 5 5 : btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump sub-routine table 53. short instructions supporting di rect, indexed, indirect and indirect indexed addressing modes (continued) short instructions only function table 54. relative direct and indi rect instructions and functions available relative direct/indirect instructions function jrxx conditional jump callr call relative table 55. instruction groups group instructions load and transfer ld clr ??? ? ?? stack operation push pop rsp ?? ? ?? increment/decrement inc dec ??? ? ?? compare and tests cp tnz bcp ?? ? ?? logical operations and or xor cpl neg ?? ? bit operation bset bres ??? ? ?? conditional bit test and branch btjt btjf ??? ? ?? arithmetic operations adc add sub sbc mul ??? shift and rotates sll srl sra rlc rrc swap sla ? unconditional jump or call jra jrt jrf jp call callr nop ret
st7lite20f2 ST7LITE25F2 st 7lite29f2 instruction set doc id 8349 rev 5 115/166 using a prebyte the instructions are described with 1 to 4 bytes. in order to extend the number of available opcodes for an 8-bit cpu (256 opcodes), three different prebyte opcodes are defined. these prebytes modify the meaning of the instruction they precede. the whole instruction becomes: pc-2: end of previous instruction pc-1: prebyte pc: opcode pc+1: additional word (0 to 2) according to the number of bytes required to compute the effective address. these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90: replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92: replace an instruction using direct, direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruction using indirect x indexed addressing mode. piy 91: replace an instruction using x indirect indexed addressing mode by a y one. 12.2.1 illegal opcode reset in order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implem ented. if a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. this, combined with the watchdog, allows the detection and recovery from an unexpected fault or interference. note: a valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset. conditional branch jrxx ???? ??? interruption management trap wfi halt iret ???? condition code flag modification sim rim scf rcf ???? table 55. instruction groups (continued) group instructions table 56. instruction set overview mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h ? nzc add addition a = a + m a m h ? nzc and logical and a = a . m a m ?? nz ?
instruction set st7lite20f2 ST7LITE25F2 st7lite29f2 116/166 doc id 8349 rev 5 bcp bit compare a, memory tst (a . m) a m ?? nz ? bres bit reset bres byte, #3 m ? ????? bset bit set bset byte, #3 m ? ????? btjf jump if bit is false (0) btjf byte, #3, jmp1 m ? ???? c btjt jump if bit is true (1) btjt byte, #3, jmp1 m ? ???? c call call sub-routine ? ? ? ????? callr call sub-routine relative ? ? ? ????? clr clear ? reg, m ??? 01 ? cp arithmetic compare ? reg m ?? nzc cpl one complement a = ffh-a reg, m ??? nz1 dec decrement dec y reg, m ??? nz ? halt halt ???? 0 ??? iret interrupt routine return pop cc, a, x, pc ?? hinzc inc increment inc x reg, m ??? nz ? jp absolute jump jp [tbl.w] ? ? ????? jra jump relative always ? ? ? ????? jrt jump relative ? ? ? ????? jrf never jump jrf * ? ? ????? jrih jump if ext. interrupt = 1 ? ? ? ????? jril jump if ext. interrupt = 0 ? ? ? ????? jrh jump if h = 1 h = 1 ? ? ? ????? jrnh jump if h = 0 h = 0 ? ? ? ????? jrm jump if i1:0 = 11 i = 1 ? ? ? ????? jrnm jump if i1:0 <> 11 i = 0 ? ? ? ????? jrmi jump if n = 1 (minus) n = 1 ? ? ? ????? jrpl jump if n = 0 (plus) n = 0 ? ? ? ????? jreq jump if z = 1 (equal) z = 1 ? ? ? ????? jrne jump if z = 0 (not equal) z = 0 ? ? ? ????? jrc jump if c = 1 c = 1 ? ? ? ????? jrnc jump if c = 0 c = 0 ? ? ? ????? jrult jump if c = 1 unsigned < ? ? ????? jruge jump if c = 0 jmp if unsigned >= ? ? ????? jrugt jump if (c + z = 0) unsigned > ? ? ????? jrule jump if (c + z = 1) unsigned <= ? ? ????? ld load dst <= src reg, m m, reg ?? nz ? table 56. instruction set overview (continued) mnemo description function/example dst src h i n z c
st7lite20f2 ST7LITE25F2 st 7lite29f2 instruction set doc id 8349 rev 5 117/166 mul multiply x,a = x * a a, x, y x, y, a 0 ??? 0 neg negate (2's compl) neg $10 reg, m ??? nzc nop no operation ? ? ? ????? or or operation a = a + m a m ?? nz ? pop pop from the stack pop reg pop cc reg cc m m ????? hinzc push push onto the stack push y m reg, cc ????? rcf reset carry flag c = 0 ? ? ???? 0 ret subroutine return ? ? ? ????? rim enable interrupts i = 0 ??? 0 ??? rlc rotate left true c c <= dst <= c reg, m ??? nzc rrc rotate right true c c => dst => c reg, m ??? nzc rsp reset stack pointer s = max allowed ? ? ????? sbc subtract with carry a = a - m - c a m ?? nzc scf set carry flag c = 1 ? ? ???? 1 sim disable interrupts i = 1 ??? 1 ??? sla shift left arithmetic c <= dst <= 0reg, m ??? nzc sll shift left logic c <= dst <= 0reg, m ??? nzc srl shift right logic 0 => dst => c reg, m ??? 0zc sra shift right arithmetic dst7 => dst => creg, m ??? nzc sub subtraction a = a - m a m ?? nzc swap swap nibbles dst[7..4] <=> dst[3..0] reg, m ??? nz ? tnz test for neg and zero tnz lbl1 ???? nz ? trap s/w trap s/w interrupt ??? 1 ??? wfi wait for interrupt ???? 0 ??? xor exclusive or a = a xor m a m ?? nz ? table 56. instruction set overview (continued) mnemo description function/example dst src h i n z c
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 118/166 doc id 8349 rev 5 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 13.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 13.1.2 typical values unless otherwise specified, typical data are based on t a =25 c, v dd =5 v (for the 4.5v v dd 5.5 v voltage range) and v dd =3.3 v (for the 3 v v dd 4 v voltage range). they are given only as design guidelines and are not tested. 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 50 . figure 50. pin loading conditions c l st7 pin
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 119/166 13.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 51 . figure 51. pin input voltage 13.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in st7 pin table 57. voltage characteristics symbol ratings maximum value unit v dd - v ss supply voltage 7.0 v v in input voltage on any pin (1) v ss - 0.3 to v dd + 0.3 v esd(hbm) electrostatic discharge voltage (human body model) see section 13.7.3: absolute maximum ratings (electrical sensitivity) v 1. directly connecting the i/o pins to v dd or v ss could damage the device if an unexpe cted change of the i/o configuration occurs (for example, due to a corrupt ed program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10 k for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current mu st be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 120/166 doc id 8349 rev 5 13.3 operating conditions 13.3.1 general operating conditions t a = -40 to +85 c unle ss otherwise specified. table 58. current characteristics symbol ratings ma ximum value unit i vdd total current into v dd power lines (source) (1) 100 ma i vss total current out of v ss ground lines (sink) (1) 100 i io output current sunk by any standard i/o and control pin 25 output current sunk by any high sink i/o pin 50 output current source by any i/os and control pin - 25 i inj(pin) (2) & (3) injected current on reset pin 5 injected current on osc1 and osc2 pins 5 injected current on pb0 and pb1 pins (4) +5 injected current on any other pin (5) 5 i inj(pin) (1) total injected current (sum of all i/o and control pins) (5) 20 1. all power (v dd ) and ground (v ss ) lines must always be connect ed to the external supply. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current mu st be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 121/166 figure 52. f cpu maximum operating frequency versus v dd supply voltage 13.3.2 operating conditions with low voltage detector (lvd) t a = -40 to 85c, unless otherwise specified table 60. general operating conditions symbol parameter conditions min max unit v dd supply voltage f cpu = 4 mhz. max. 2.4 5.5 v f cpu = 8 mhz. max. 3.3 5.5 f cpu cpu clock frequency 3.3 v v dd 5.5 v up to 8 mhz 2.4 v v dd < 3.3 v up to 4 f cpu [mhz] supply voltage [v] 8 4 2 0 2.0 2.4 3.33.54.04.55.0 functionality not guaranteed in this area 5.5 functionality guaranteed in this area (unless otherwise stated in the tables of parametric data) 2.7 table 61. power on/power down operating conditions symbol parameter conditions min typ max unit v it+ (lvd) reset release threshold (v dd rise) high threshold med. threshold low threshold 4.00 (1) 3.40 (1) 2.65 (1) 1. not tested in production. 4.25 3.60 2.90 4.50 3.80 3.15 v v it- (lvd) reset generation threshold (v dd fall) high threshold med. threshold low threshold 3.80 3.20 2.40 4.05 3.40 2.70 4.30 (1) 3.65 (1) 2.90 (1) v hys lvd voltage threshold hysteresis v it+ (lvd) -v it- (lvd) ? 200 ? mv vt por v dd rise time rate (2) 2. not tested in production. the v dd rise time rate condition is needed to insure a correct device power-on and lvd reset. when the v dd slope is outside these values, the lv d may not ensure a proper reset of the mcu. use of lvd with capacitive power s upply: with this type of power supply, if power cuts occur in the application, it is recommended to pull v dd down to 0 v to ensure optimum restart conditions. refer to circuit example in figure 84: reset pin protection when lvd is enabled ? 20 20000 s/v t g(vdd) filtered glitch delay on v dd not detected by the lv d ?? 150 ns i dd(lvd ) lvd/avd current consumption ?? 220 ? a
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 122/166 doc id 8349 rev 5 13.3.3 auxiliary voltage de tector (avd) thresholds t a = -40 to 85c, unless otherwise specified. 13.3.4 internal rc oscillator and pll the st7 internal clock can be supplied by an internal rc o scillator and pll (selectable by option byte). the rc oscillator and pll characteristics ar e temperature-dependent and are grouped in four tables. table 62. avd thresholds symbol parameter conditions min typ max unit v it+ (avd) 1=>0 avdf flag toggle threshold (v dd rise) high threshold med. threshold low threshold 4.40 (1) 3.90 (1) 3.20 (1) 4.70 4.10 3.40 5.00 4.30 3.60 v v it- (avd) 0=>1 avdf flag toggle threshold (v dd fall) high threshold med. threshold low threshold 4.30 3.70 2.90 4.60 3.90 3.20 4.90 (1) 4.10 (1) 3.40 (1) v hys avd voltage threshold hysteresis v it+ (avd) -v it- (avd) ? 150 ? mv v it- voltage drop between avd flag set and lvd reset activation v dd fall ? 0.45 ? v 1. not tested in production. table 63. internal rc oscillator and pll symbol parameter min typ max unit v dd(rc) internal rc oscillator operating voltage 2.4 ? 5.5 v v dd(x4pll) x4 pll operating voltage 2.4 ? 3.3 v dd(x8pll) x8 pll operating voltage 3.3 ? 5.5 t startup pll startup time ? 60 ? pll input clock (f pll ) cycles table 64. rc oscillator and pll characteristics (tested for t a = -40 to +85c) @ v dd =4.5to 5.5 v symbol parameter conditions min typ max unit f rc (1) internal rc oscillator frequency (1) rccr = ff (reset value), t a =25 c, v dd =5 v ? 760 ? khz rccr = rccr0 (2) , t a =25 c, v dd =5 v ? 1000 ? acc rc accuracy of internal rc oscillator with rccr=rccr0 (2) t a =25 c, v dd =4.5 to 5.5 v -1 ? + 1% t a =-40 to +85 c, v dd =5 v -5 ? +2 % t a =0 to +85 c, v dd =4.5 to 5.5 v -2 (3) ? +2 (3) %
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 123/166 i dd(rc) rc oscillator current consumption t a =25 c, v dd =5 v ? 970 (3) ? a t su(rc) rc oscillator setup time t a =25 c, v dd =5 v ?? 10 (2) s f pll x8 pll input clock ?? 1 (3) ? mhz t lock pll lock time (4) ?? 2 ? ms t stab pll stabilization time (4) ?? 4 ? ms acc pll x8 pll accuracy f rc = 1 mhz@t a =25 c, v dd =4.5 to 5.5 v ? 0.1 (5) ? % f rc = 1 mhz@t a =-40 to +85 c, v dd =5 v ? 0.1 (5) ? % t w(jit) pll jitter period f rc = 1 mhz ? 125 (6) ? s jit pll pll jitter ( f cpu /f cpu ) ?? 1 (6) ? % i dd(pll) pll current consumption t a =25 c ? 600 (3) ? a 1. if the rc oscillator clock is select ed, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nf, between the v dd and v ss pins as close as possi ble to the st7 device. 2. see section 7.1: internal rc oscillator adjustment . 3. data based on characterization results, not tested in production. 4. after the locked bit is set acc pll is max. 10% until t stab has elapsed. see figure 12: pll output frequency timing diagram . 5. averaged over a 4ms period. after t he locked bit is set, a period of t stab is required to reach acc pll accuracy. 6. guaranteed by design. table 64. rc oscillator and pll characteristics (tested for t a = -40 to +85c) @ v dd =4.5to 5.5 v (continued) symbol parameter conditions min typ max unit table 65. rc oscillator and pll characteristics (tested for ta = -40 to +85c) @ vdd = 2.7 to 3.3v symbol parameter conditions min typ max unit f rc (1) internal rc oscillator frequency (1) rccr = ff (reset value), t a =25 c, v dd = 3.0v ? 560 ? khz rccr=rccr1 (3) ,t a =25c, v dd = 3 v ? 700 ? acc rc accuracy of internal rc oscillator when calibrated with rccr=rccr1 (2)(3) t a =25c,v dd =3v -2 ? +2 % t a =25c,v dd =2.7 t 3.3v -25 ? +25 % t a =-40 to +85c,v dd =3v -15 ? 15 % i dd(rc) rc oscillator current consumption t a =25c,v dd =3v ? 700 (2) ? a t su(rc) rc oscillator setup time t a =25c,v dd =3v ?? 10 (3) s f pll x4 pll input clock ?? 0.7 (2) ? mhz t lock pll lock time (4) ?? 2 ? ms t stab pll stabilization time (4) ?? 4 ? ms acc pll x4 pll accuracy f rc = 1mhz@t a =25c,v dd =2.7 to 3.3v ? 0.1 (5) ? % f rc = 1mhz@t a =40 to +85c,v dd = 3v ? 0.1 (5) ? % t w(jit) pll jitter period f rc = 1mhz ? 125 (6) ? s
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 124/166 doc id 8349 rev 5 figure 53. rc osc freq vs v dd @ t a = 25c (calibrated with rccr1: 3v @ 25c) figure 54. rc osc freq vs v dd (calibrated with rccr0: 5v@ 25c) figure 55. typical rc oscillator accuracy vs temperature @ v dd =5v (calibrated with rccr0: 5v @ 25c ) jit pll pll jitter ( f cpu /f cpu ) ?? 1 (6) ? % i dd(pll) pll current consumption t a =25c ? 190 (2) ? a 1. if the rc oscillator clock is selected, to improve clock stability and frequency ac curacy, it is recommended to place a decoupling capacitor, typically 100nf, between the v dd and v ss pins as close as possi ble to the st7 device. 2. data based on characterization results, not tested in production. 3. see section 7.1: internal rc oscillator adjustment . 4. after the locked bit is set acc pll is max. 10% until t stab has elapsed. see figure 12: pll output frequency timing diagram . 5. averaged over a 4ms period. after t he locked bit is set, a period of t stab is required to reach acc pll accuracy. 6. guaranteed by design. table 65. rc oscillator and pll characteristics (tested for ta = -40 to +85c) @ vdd = 2.7 to 3.3v (continued) symbol parameter conditions min typ max unit 0.50 0.60 0.70 0.80 0.90 1.00 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 vdd (v) output freq (mhz ) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 2.5 3 3.5 4 4.5 5 5.5 6 vdd (v) output freq. (mhz) -45 0 25 90 105 130 2 -1 -5 -45 025 85 -2 -4 -3 0 1 ( * ) ( * ) ( * ) ( * ) tested in production temperature (c) rc accuracy 125
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 125/166 figure 56. rc osc freq vs v dd and rccr value figure 57. pll f cpu /f cpu versus time figure 58. pllx4 output vs clkin frequency 1. f osc = f clkin /2*pll4 figure 59. pllx8 output vs clkin frequency 1. f osc = f clkin /2*pll8 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.4 2.7 3 3.3 3.75 4 4.5 5 5.5 6 vdd (v) output freq. (mhz) rccr=00h rccr=64h rccr=80h rccr=c0h rccr=ffh t w(jit) f cpu /f cpu t min max 0 t w(jit) 1.00 2.00 3.00 4.00 5.00 6.00 7.00 1 1.5 2 2.5 3 external input clock frequency (mhz) output frequency (mhz) 3.3 3 2.7 1.00 3.00 5.00 7.00 9.00 11.00 0.85 0.9 1 1.5 2 2.5 external input clock frequency (mhz) output frequency (mhz) 5.5 5 4.5 4
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 126/166 doc id 8349 rev 5 note: t a = -40 to 85c, unless otherwise specified. 13.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consumption, the two current values must be added (except for halt mode for which the clock is stopped). note: ta = -40 to +85c unle ss otherwise specified, v dd =5.5v. table 66. 32mhz pll symbol parameter min typ max unit v dd voltage (1) 1. 32 mhz is guaranteed within this voltage range. 4.5 5 5.5 v f pll32 frequency (1) ? 32 ? mhz f input input frequency 7 8 9 mhz table 67. supply current symbol parameter conditions typ max unit i dd supply current in run mode external clock, f cpu = 1mhz (1) 1 ? ma internal rc, f cpu =1mhz 2.2 ? f cpu =8mhz (1) 7.5 12 supply current in wait mode external clock, f cpu =1mhz (2) 0.8 ? internal rc, f cpu =1mhz 1.8 ? f cpu = 8mhz (2) 3.7 6 supply current in slow mode f cpu = 250khz (3) 1.6 2.5 supply current in slow-wait mode f cpu = 250khz (4) 1.6 2.5 supply current in halt mode (5) -40c t a +85c 1 10 a t a = +125c 15 50 supply current in awuf mode (6) t a = +25c 20 30 1. cpu running with memory access , all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 2. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in re set state; clock input (clkin) driven by external sq uare wave, lvd disabled. 3. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in i nput mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 4. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in i nput mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 5. all i/o pins in output mode with a static value at v ss (no load), lvd disabled. data based on characterization results, tested in production at v dd max and fcpu max. 6. all i/o pins in input mode with a static value at vdd or vss (no load). data tested in production at vdd max. and fcpu max. this consumption refers to the halt period only and not the associated run period which is software dependent.
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 127/166 figure 60. typical i dd in run vs. f cpu figure 61. typical i dd in slow vs. f cpu figure 62. typical i dd in wait vs. f cpu figure 63. typical i dd in slow-wait vs. f cpu figure 64. typical i dd in awuf mode at t a = 25c 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (v) idd (ma) 8mhz 4mhz 1mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd (v) idd (ma) 250khz 125khz 62.5hz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (v) idd (ma) 8mhz 4mhz 1mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.02.53.03.54.04.55.05.56.0 vdd (v) idd (ma) 250khz 125khz 62.5khz 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd(v) idd(ma) fawu_rc ~125 khz
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 128/166 doc id 8349 rev 5 figure 65. typical i dd vs. temperature at v dd = 5v and f cpu = 8mhz 13.5 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . table 68. on-chip peripherals symbol parameter conditions typ unit i dd(at) 12-bit auto-reload timer supply current (1) 1. data based on a differential i dd measurement between reset confi guration (timer stopped) and a timer running in pwm mode at f cpu = 8mhz. f cpu =4mhz v dd = 3.0v 300 a f cpu =8mhz v dd = 5.0v 1000 i dd(spi) spi supply current (2) 2. data based on a differential i dd measurement between reset configuration and a permanent spi master communication (data sent equal to 55h). f cpu =4mhz v dd = 3.0v 50 f cpu =8mhz v dd = 5.0v 300 i dd(adc) adc supply current when converting (3) 3. data based on a differential i dd measurement between reset configuration and continuous a/d conversions with amplifier off. f adc =4mhz v dd = 3.0v 250 v dd = 5.0v 1100 2.0 3.0 4.0 5.0 6.0 7.0 8.0 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 vdd (v) idd (ma) 25 -45 90 130 table 69. general timings symbol parameter (1) 1. guaranteed by design. not tested in production. conditions min typ (2) 2. data based on typical application software. max unit t c(inst) instruction cycle time f cpu =8mhz 2312t cpu 250 375 1500 ns t v(it) interrupt reaction time (3) t v(it) = t c(inst) + 10 3. time measured between interrupt event and interrupt vector fetch. dt c(inst) is the number of t cpu cycles needed to finish the current instruction execution. f cpu =8mhz 10 ? 22 t cpu 1.25 ? 2.75 s
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 129/166 13.5.1 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with eight different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possibl e to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to t he crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). table 72. resonator performances table 70. auto wakeup from halt oscillator (awu) symbol parameter (1) 1. guaranteed by design. conditions min typ max unit f awu awu oscillator frequency ? 50 125 250 khz t rcsrt awu oscillator startup time ??? 50 s table 71. resonator characteristics symbol parameter conditions min typ max unit f crosc crystal oscillator frequency (1) 1. when pll is used, please refer to the section 13.3.4: internal rc oscillator and pll and section 7: supply, reset and clock management (fcrosc min. is 8 mhz with pll). ? 2 ? 16 mhz c l1 c l2 recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (r s ) ? see table 72: resonator performances pf supplier f crosc [mhz] typical ceramic resonators (1) 1. resonator characteri stics given by the ceramic resonator manufacturer. for more information on these resonators, please consult www.murata.com cl1 (2) [pf] 2. () means load capaci tor built in resonator. cl2 (2) [pf] rd [ ] supply voltage range [v] temperature range [c] type (3) 3. smd = -r0: plastic tape package ( ? =180mm). lead = -b0: bulk reference murata 2 smd cstcc2m00g56-r0 (47) (47) 0 2.4v to 5.5v -40 to 85 4 smd cstcr4m00g53-r0 (15) (15) 0 lead cstls4m00g53-b0 (15) (15) 0 8 smd cstce8m00g52-r0 (10) (10) 0 lead cstls8m00g53-b0 (15) (15) 0 16 smd cstce16m0v51-r0 (5) (5) 0 3.3v to 5.5v lead cstls16m0x53-b0 (15) (15) 0 4.5v to 5.5v lead csals16m0x55-b0 7 7 1.5k 3.8v to 5.5v
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 130/166 doc id 8349 rev 5 figure 66. typical application with a crystal or ceramic resonator 13.6 memory characteristics t a = -40c to 85c, unless otherwise specified. osc2 osc1 f osc c l1 c l2 i 2 resonator when resonator with integrated capacitors r d st7lite2 table 73. ram and hardware registers symbol parameter cond itions min typ max unit v rm data retention mode (1) halt mode (or reset) 1.6 ?? v 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by co nstruction, not tested in production. table 74. flash program memory symbol parameter conditions min typ max unit v dd operating voltage for flash write/erase ? 2.4 ? 5.5 v t prog programming time for 1~32 bytes (1) t a =? 40 to +85c ? 510ms programming time for 1.5 kbytes t a = +25c 0.24 0.48 s t ret data retention (2) t a = +55c (3) 20 ?? years n rw write erase cycles t a = +25c 10k (4) ?? cycles i dd supply current read / write / erase modes f cpu = 8mhz, v dd = 5.5v ?? 2.6 (5) ma no read/no write mode ?? 100 a power down mode / halt ? 00.1 a 1. up to 32 bytes can be programmed at a time. 2. data based on reliability test results and monitored in production. 3. the data retention time increases when the t a decreases. 4. design target value pending full product characterization. 5. guaranteed by design. not tested in production.
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 131/166 13.7 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 13.7.1 functional ems (elect ro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic ev ents until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the ta bl e 7 6 based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) table 75. eeprom data memory symbol parameter conditions min typ max unit v dd operating voltage for eeprom write/erase ? 2.4 ? 5.5 v t prog programming time for 1~32 bytes t a =? 40 to +85c ? 510ms t ret data retention (1) t a =+55c (2) 20 ?? years n rw write erase cycles t a = +25c 300k (3) ?? cycles 1. data based on reliability test results and monitored in production. 2. the data retention time increases when the t a decreases. 3. design target value pending full product characterization.
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 132/166 doc id 8349 rev 5 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. note: for more details, refer to the application note an1015. 13.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the boar d and the loading of each pin. note: data based on characterization results, not tested in production. 13.7.3 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. note: for more details, refer to the application note an1181. electro-static discharge (esd) electro-static discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a114a/a115a standard. table 76. test results symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 3b v fftb fast transient voltage burst limits to be applied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-4 3b table 77. emission test symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ]unit 8/4mhz 16/8mhz ? s emi peak level v dd = 5v, t a = +25c, so20 package, conforming to sae j 1752/3 0.1 mhz to 30 mhz 9 17 db v 30 mhz to 130 mhz 31 36 130 mhz to 1 ghz 25 27 sae emi level 3.5 4 ?
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 133/166 static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the mi cro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards. note: for more details, refer to the application note an1181. 13.8 i/o port pin characteristics table 78. absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 4000 v table 79. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). lu static latch-up class t a = +25c a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a table 80. general characteristics (1) symbol parameter conditions min typ max unit v il input low level voltage ? v ss - 0.3 ? 0.3 x v dd v v ih input high level voltage ? 0.7 x v dd ? v dd + 0.3 v hys schmitt trigger voltage hysteresis (2) ?? 400 ? mv i l input leakage current v ss v in v dd ?? 1 a i s static current consumption induced by each floating input pin (3) floating input mode ? 400 ? r pu weak pull-up equivalent resistor (4) v in = v ss v dd =5v 50 120 250 k v dd =3v ? 160 ? c io i/o pin capacitance ?? 5 ? pf
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 134/166 doc id 8349 rev 5 figure 67. two typical applications with unused i/o pin caution: to avoid entering icc mode unexpectedly during a reset, the iccclk pin must be pulled-up internally or externally during normal operation (external pull-up of 10k mandatory in noisy environment). note: i/o can be left unconnected if it is configured as output (0 or 1) by the software. this has the advantage of greater emc robustness and lower cost. figure 68. typical i pu vs. v dd with v in =v ss t f(io)out output high to low level fall time (2) c l =50pf between 10% and 90% ? 25 ? ns t r(io)out output low to high level rise time (2) ? 25 ? t w(it)in external interrupt pulse time (5) ? 1 ?? t cpu 1. subject to general ope rating conditions for v dd , f osc , and t a unless otherwise specified. 2. data based on characterization results, not tested in production. 3. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull- up or pull-down resistor (see figure 67 ). static peak current value taken at a fixed v in value, based on design simulation and technology characteristics, not tested in pr oduction. this value depends on v dd and temperature values. 4. the r pu pull-up equivalent resistor is based on a resistive transis tor (corresponding i pu current characteristics described in figure 68 ). 5. to generate an external interrupt, a mini mum pulse width has to be applied on an i/o port pin configured as an external interrupt source. table 80. general characteristics (1) (continued) symbol parameter conditions min typ max unit 10k unused i/o port st7xxx 10k unused i/o port st7xxx v dd 0 10 20 30 40 50 60 70 80 90 22.533.5 44.555.56 vdd(v) ip u (ua ) ta=140c ta=95c ta=25c ta=-45c
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 135/166 figure 69. typical v ol at v dd = 2.4v (standard) table 81. output driving current (1) symbol parameter conditions min max unit v ol (2) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 72 ) v dd =5v i io =+5ma t a 85c t a 85c 1.0 1.2 v i io =+2ma t a 85c t a 85c 0.4 0.5 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 74 ) i io =+20ma t a 85c t a 85c 1.3 1.5 i io =+8ma t a 85c t a 85c 0.75 0.85 v oh (3) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 80 ) i io =-5ma t a 85c t a 85c v dd -1.5 v dd -1.6 i io =-2ma t a 85c t a 85c v dd -0.8 v dd -1.0 v ol (2)(4) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 71 ) v dd =3.3v i io =+2ma t a 85c t a 85c 0.5 0.6 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time i io =+8ma t a 85c t a 85c 0.5 0.6 v oh (3)(4) output high level voltage for an i/o pin when 4 pins are sourced at same time i io =-2ma t a 85c t a 85c v dd -0.8 v dd -1.0 v ol (2)(4) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 69 ) v dd =2.7v i io =+2ma t a 85c t a 85c 0.6 0.7 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time i io =+8ma t a 85c t a 85c 0.6 0.7 v oh (3)(4) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 77 ) i io =-2ma t a 85c t a 85c v dd -0.9 v dd -1.0 1. subject to general ope rating conditions for v dd , f osc , and t a unless otherwise specified. 2. the i io current sunk must always respect the absolute maximum rating specified in table 58: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vss . 3. the i io current sourced must always respect the absolute maximum rating specified in table 58: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vdd . 4. not tested in production, based on characterization results. 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.01 1 2 lio (ma) vol at vdd=2.4v -45 0c 25c 90c 130c
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 136/166 doc id 8349 rev 5 figure 70. typical v ol at v dd = 2.7v (standard) figure 71. typical v ol at v dd = 3.3v (standard) figure 72. typical v ol at v dd = 5v (standard) figure 73. typical v ol at v dd = 2.4v (high-sink) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.01 1 2 lio (ma) vol at vdd=2.7v -45c 0c 25c 90c 130c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.01 1 2 3 lio (ma) vol at vdd=3.3v -45c 0c 25c 90c 130c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.0112345 lio (ma) vol at vdd=5v -45c 0c 25c 90c 130c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 678910 lio (ma) vol at vdd=2.4v (hs) -45 0c 25c 90c 130c
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 137/166 figure 74. typical v ol at v dd = 5v (high-sink) figure 75. typical v ol at v dd = 3v (high-sink) figure 76. typical v dd -v oh at v dd = 2.4v figure 77. typical v dd -v oh at v dd = 2.7v 0.00 0.50 1.00 1.50 2.00 2.50 6 7 8 9 10 15 20 25 30 35 40 lio (ma) -45 0c 25c 90c 130c 0.00 0.20 0.40 0.60 0.80 1.00 1.20 67891015 lio (ma) vol (v) at vdd=3v (hs) -45 0c 25c 90c 130c 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 -0.01 -1 -2 lio (ma) vdd-voh at vdd=2.4v -45c 0c 25c 90c 130c 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -0.01 -1 -2 lio(ma) vdd-voh at vdd=2.7v -45c 0c 25c 90c 130c
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 138/166 doc id 8349 rev 5 figure 78. typical v dd -v oh at v dd = 3v figure 79. typical v dd -v oh at v dd =4v figure 80. typical v dd -v oh at v dd =5v figure 81. v ol vs. v dd (standard i/os) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 -0.01-1-2-3 lio (ma) vdd-voh at vdd=3v -45c 0c 25c 90c 130c 0.00 0.50 1.00 1.50 2.00 2.50 -0.01-1-2-3-4 -5 lio (ma) vdd-voh at vdd=4v -45c 0c 25c 90c 130c 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 -0.01-1-2-3-4-5 lio (ma) vdd-voh at vdd=5v -45c 0c 25c 90c 130c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 2.4 2.7 3.3 5 vdd (v) vol (v) at lio=2ma -45 0c 25c 90c 130c 0.00 0.01 0.02 0.03 0.04 0.05 0.06 2.4 2.7 3.3 5 vdd (v) vol (v) at lio=0.01ma -45 0c 25c 90c 130c
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 139/166 figure 82. typical v ol vs. v dd (high-sink i/os) figure 83. typical v dd -v oh vs. v dd 13.9 control pin characteristics 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 2.4 3 5 vdd (v) vol vs vdd (hs) at lio=8ma -45 0c 25c 90c 130c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 2.4 3 5 vdd (v) vol vs vdd (hs) at lio=20ma -45 0c 25c 90c 130c 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 2.4 2.7 3 4 5 vdd (v) vdd-voh (v) at lio=-2ma -45c 0c 25c 90c 130c 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 45 vdd vdd-voh at lio=-5ma -45c 0c 25c 90c 130c table 82. asynchronous reset pin (1) symbol parameter condi tions min typ max unit v il input low level voltage ? v ss - 0.3 ? 0.3xv dd v v ih input high level voltage ? 0.7xv d d ? v dd + 0.3 v hys schmitt trigger voltage hysteresis (2) ?? 2 ? v v ol output low level voltage (3) v dd =5v i io =+5ma t a 85c t a 85c ? 0.5 1.0 1.2 v i io =+2ma t a 85c t a 85c ? 0.2 0.4 0.5 r on pull-up equivalent resistor (2)(4) v dd =5v 20 40 80 k v dd =3v 40 70 120 t w(rstl)out generated reset pulse duration internal reset sources ? 30 ? s t h(rstl)in external reset pulse hold time (5) ? 20 ?? s t g(rstl)in filtered glitch duration ?? 200 ? ns 1. ta = -40c to 85c, unless otherwise specified. 2. data based on characterization results, not tested in production.
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 140/166 doc id 8349 rev 5 figure 84. reset pin protection when lvd is enabled figure 85. reset pin protection when lvd is disabled the reset network protects the device against parasitic resets. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). whatever the reset source is (internal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in table 82: asynchronous reset pin . otherwise the reset will not be taken into account internally. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in table 58: current characteristics . when the lvd is enabled, it is recommended not to connect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to filter noise on the reset line. in case a capacitive power supply is used, it is recommended to connect a 1m pull-down resistor to the reset pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5a to the power consumption of the mcu). tips when using the lvd: 3. the i io current sunk must always respect t he absolute maximum rating and the sum of i io (i/o ports and control pins) must not exceed i vss . 4. the r on pull-up equivalent resistor is based on a resistive transistor. specified for voltages on reset pin between v ilmax and v dd . 5. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl) in can be ignored. 0.01 f st72xxx pulse generator filter r on v dd internal reset reset external required 1m optional (note 3) watchdog lvd reset illegal opcode 0.01 f external reset circuit user required st72xxx pulse generator filter r on v dd internal reset watchdog illegal opcode
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 141/166 1. check that all recommendations related to iccclk and reset circuit have been applied (see table 2: device pin description ) 2. check that the power supply is properly decoupled (100nf + 10f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100nf + 1m pull-down on the reset pin. 3. the capacitors connected on the reset pin and also the power supply are key to avoid any startup marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. othe rwise: replace 10nf pull-down on the reset pin with a 5f to 20f capacitor.? note: please refer to section 12.2.1: illegal opcode reset for more details. 13.10 communication interface characteristics 13.10.1 serial peripheral interface (spi) subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). table 83. serial peripheral interface (spi) (1) 1. subject to general oper ating conditions for v dd , f osc , and t a unless otherwise specified. symbol parameter conditions min max unit f sck = 1/t c(sck) spi clock frequency master f cpu = 8mhz f cpu /128 = 0.0625 f cpu /4 = 2 mhz slave f cpu = 8mhz 0f cpu /2 = 4 t r(sck) t f(sck) spi clock rise and fall time ? see i/o port pin description t su(ss ) (2) 2. data based on design simulation and/or charac terization results, not tested in production. ss setup time (3) slave (4 x t cpu ) +150 ? ns t h(ss ) (2) ss hold time slave 120 ? t w(sckh) t w(sckl) sck high and low time master slave 100 90 ? t su(mi) t su(si) data input setup time master slave 100 100 ? t h(mi) t h(si) data input hold time master slave 100 100 ? t a(so) data output access time slave 0 120 t dis(so) data output disable time slave ? 240 t v(so) data output valid time slave (after enable edge) ? 120 t h(so) data output hold time 0 ? t v(mo) data output valid time master (after enable edge) ? 120 t h(mo) data output hold time 0 ?
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 142/166 doc id 8349 rev 5 figure 86. spi slave timi ng diagram with cpha = 0 (1) 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, t he pin status depends on the i/o port configuration. figure 87. spi slave timing diagram with cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, t he pin status depends on the i/o port configuration. 3. depends on f cpu . for example, if f cpu = 8mhz, then t cpu = 1/ f cpu = 125ns and t su(ss ) = 550ns ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) bit1 in (2) (2) ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) (2) t c(sck) hz t v(so) msb in lsb in bit1 in (2)
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 143/166 figure 88. spi master timing diagram (1) 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, t he pin status depends on the i/o port configuration. 13.11 10-bit adc characteristics ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in (2) (2) cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck) table 84. 10-bit adc characteristics (1) 1. subject to general operating condition for v dd , f osc , and t a unless otherwise specified. symbol parameter conditions min typ (2) 2. unless otherwise specified, typical data are based on t a =25c and v dd -v ss =5v. they are given only as design guidelines and are not tested. max unit f adc adc clock frequency ??? 4mhz v ain conversion voltage range (3) 3. when v dda and v ssa pins are not available on t he pinout, the adc refers to v dd and v ss . ? v ssa ? v dda v r ain external input resistor ??? 10 (4) 4. any added external serial resistor will downgrade the adc accuracy (es pecially for resist ance greater than 10k ) . data based on characterization re sults, not tested in production. k c adc internal sample and hold capacitor ?? 6 ? pf t stab stabilization time after adc enable f cpu =8mhz, f adc =4mhz 0 (5) s t adc conversion time (sample+hold) 3.5 - sample capacitor loading time - hold conversion time 4 10 1/f adc i adc analog part ??? 1 ma digital part ??? 0.2
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 144/166 doc id 8349 rev 5 figure 89. typical application with adc 5. the stabilization time of the ad converter is masked by the first t load . the first conversion after the enable is then always valid. table 85. adc accuracy with v dd =5.0v symbol parameter conditions typ max (1) 1. data based on characterization results over t he whole temperature range, not tested in production. unit | e t | total unadjusted error (2) 2. injecting negative current on any of the analog input pins significantly reduc es the accuracy of any conversion being performed on any analog input. analog pins can be protected against negative injecti on by adding a schottky diode (pin to ground). injecting negative current on digita l input pins degrades adc accuracy especially if performed on a pin close to the analog input pins. any positive injection current with in the limits specified for i inj(pin) and iinj(pin) in section 13.8: i/o port pin characteristics does not affect the adc accuracy. f cpu =8mhz, f adc =4mhz (1) , vdd=5.0v 36 lsb | e o | offset error (2) 1.5 5 | e g | gain error (2) 24.5 | e d | differential linearity error (2) 2.5 4.5 | e l | integral linearity error (2) 2.5 4.5 ainx st72xxx v dd i l 1 a v t 0.6v v t 0.6v c adc 6pf v ain r ain 10-bit a/d conversion c ain
st7lite20f2 ST7LITE25F2 st7lite29f2 electrical characteristics doc id 8349 rev 5 145/166 figure 90. adc accuracy characterist ics with amp lifier disabled e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. figure 91. adc accuracy characterist ics with amp lifier enabled note: when the ampsel bit in th e adcdrl register is set, it is mandatory that f adc be less than or equal to 2 mhz (if f cpu =8mhz, then speed=0, slow=1). e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dd v ss digital result adcdr e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line digital result adcdr 704 108 0 1234567 701 702 703 704 (1) (2) e t e d e l (3) v ss 430mv 62.5mv v in (opamp)
electrical characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 146/166 doc id 8349 rev 5 figure 92. amplifier noise vs voltage 13.11.1 amplifier output offset variation the offset is quite sensitive to temperature variations. in order to ensure a good reliability in measurements, the offset must be recalibrated periodically i.e. during power on or whenever the device is reset depending on the customer application and during temperature variation. ta bl e 8 7 gives the typical offset variation over temperature. table 86. adc characteristics (1) 1. data based on characterization results over t he whole temperature range, not tested in production. symbol parameter conditions min typ max unit v dd(amp) amplifier operating voltage ? 3.6 ? 5.5 v v in amplifier input voltage (2) 2. please refer to the application note an1830 for details of te% vs v in . v dd =3.6v 0 ? 350 mv v dd =5v 0 ? 500 v offset amplifier output offset voltage (3) 3. refer to the offset variation in temperature below. v dd =5v ? 200 ? mv v step step size for monotonicity (4) 4. monotonicity guaranteed if v in increases or decreases in steps of min. 5mv. v dd =3.6v 3.5 ?? mv v dd =5v 4.89 ?? linearity output voltage response ? linear gain factor amplified analog input gain (5) 5. for precise conversion results, it is recommended to calibrate the amplifier at the following two points: ? offset at v inmin = 0v ? gain at full scale (for example v in =430mv). ?? 8 ?? vmax output linearity max voltage v inmax = 430mv, v dd =5v ? 3.65 3.94 v vmin output linearity min voltage ? 200 ? mv vin vout (adc input) vmax vmin 430mv 0v noise (opamp input) table 87. typical offset variation over temperature typical offset variation (lsb) unit -45 -20 +25 +90 c -12 -7 ? +13 lsb
st7lite20f2 ST7LITE25F2 st7lite29f2 package characteristics doc id 8349 rev 5 147/166 14 package characteristics 14.1 package mechanical data figure 93. 20-pin plastic small outline package, 300-mil width table 88. small outline package characteristics dim. mm inches min typ max min typ max a 2.35 ? 2.65 0.093 ? 0.104 a1 0.10 ? 0.30 0.004 ? 0.012 b 0.33 ? 0.51 0.013 ? 0.020 c 0.23 ? 0.32 0.009 ? 0.013 d 12.60 ? 13.00 0.496 ? 0.512 e 7.40 ? 7.60 0.291 ? 0.299 e ? 1.27 ?? 0.050 ? h 10.00 ? 10.65 0.394 ? 0.419 h 0.25 ? 0.75 0.010 ? 0.030 0 ? 8 0 ? 8 l 0.40 ? 1.27 0.016 ? 0.050 number of pins n 20 eh a a1 b e d c h x 45 l a
package characteristics st7lite20f2 ST7LITE25F2 st7lite29f2 148/166 doc id 8349 rev 5 figure 94. 20-pin plastic dual in-line package, 300-mil width table 89. dual in-line package characteristics dim. mm inches min typ max min typ max a ?? 5.33 ?? 0.210 a1 0.38 ?? 0.015 ?? a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 d 24.89 26.16 26.92 0.980 1.030 1.060 d1 0.13 ?? 0.005 ?? e ? 2.54 ?? 0.100 ? eb ?? 10.92 ?? 0.430 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150 number of pins n 20 e1 d d1 b e a a1 l a2 c eb 11 10 1 20 b2
st7lite20f2 ST7LITE25F2 st7lite29f2 package characteristics doc id 8349 rev 5 149/166 14.2 soldering information in accordance with the rohs european directive, all stmicroelectronics packages have been converted to lead-free technology, named ecopack tm . ecopack tm packages are qualified according to the jedec std-020c compliant soldering profile. detailed information on the stmicroelectronics ecopack tm transition program is available on www.st.com/stonline/leadfree/, with specific technical application notes covering the main technical aspects related to lead-free conversion (an2033, an2034, an2035, an2036). backward and forward compatibility the main difference between pb and pb-free soldering process is the temperature range. ecopack tm tqfp, sdip and so packages are fully compatible with lead (pb) containing soldering process (see application note an2034) tqfp, sdip and so pb-packages are compatible with lead-free soldering process, nevertheless it's the customer's duty to verify that the pb packages maximum temperature (mentioned on the inner box label) is compatible with their leadfree soldering temperature. table 90. thermal characteristics symbol ratings value unit r thja package thermal resistance (junction to ambient) so20 dip20 125 63 c/w t jmax maximum junction temperature (1) 1. the maximum chip-junction temperature is based on technology characteristics. 150 c p dmax power dissipation (2) 2. the maximum power dissipation is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an application can be defined by the user with the formula: p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation depending on the ports used in the application. 500 mw table 91. soldering compatibility (w ave and reflow soldering process) package plating material devices pb solder paste pb-free solder paste sdip & pdip sn (pure tin) yes yes (1) 1. assemblers must verify that the pb-package maxi mum temperature (mentioned on the inner box label) is compatible with their lead-free soldering process. tqfp and so nipdau (nickel-palladium-gold) yes yes (1)
device configuration st7lite20f2 ST7LITE25F2 st7lite29f2 150/166 doc id 8349 rev 5 15 device configuration each device is available for production in user programmable versions (flash) as well as in factory coded versions (fastrom). st7flite2 devices are flash versions. st7plite2 devices are factory advanced service technique rom (fastrom) versions: they are factory programmed flash devices. st7flite2 devices are shipped to customers with a default program memory content (ffh), while fastrom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the customer using the option bytes while the fastrom devices are factory configured. 15.1 option bytes the two option bytes allow the hardware configuration of the microcontroller to be selected. the option bytes can be accessed only in programming mode (for example using a standard st7 programming tool). 15.1.1 option byte 0 opt7 = reserved, must always be 1 opt6:4 = oscrange[2:0] oscillator range when the internal rc oscillator is not se lected (option osc=1) , these option bits select the range of th e resonator oscillator cu rrent source or the external clock source. note: when the internal rc oscillator is selected , the oscrange option bits must be kept at their default value in order to select the 256 clock cycle delay (see section 7.5: reset sequence manager (rsm) ). opt3:2 = sec[1:0] sector 0 size definition these option bits indicate the size of sector 0 according to ta b l e 9 3 . table 92. option bytes values oscrange 210 ty p. frequency range with resonator lp 1~2mhz 0 0 0 mp 2~4mhz 0 0 1 ms 4~8mhz 0 1 0 hs 8~16mhz 0 1 1 vlp 32.768khz 1 0 0 external clock source: clkin on osc1 1 0 1 on pb4 1 1 1 reserved 1 1 0
st7lite20f2 ST7LITE25F2 st7lite29f2 device configuration doc id 8349 rev 5 151/166 opt1 = fmp_r read-out protection read-out protection, when selected provides a protection against program memory content extraction and against write access to flash memory. erasing the option bytes when the fmp_r option is selected will cause the whole memory to be erased first and the device can be reprogrammed. refer to the st7 flash programming reference manual and section 4.5: memory protection for more details 0: read-out protection off 1: read-out protection on opt0 = fmp_w flash write protection this option indicates if the flash program memory is write protected. 0: write protection off 1: write protection on warning: when this option is select ed, the program memory (and the option bit itself) can never be erased or programmed again. table 93. size definition sector 0 size sec1 sec0 0.5k 00 1k 01 2k 10 4k 11 table 94. option byte default values option byte 0 70 option byte 1 70 res. oscrange 2:0 sec 1 sec 0 fmp r fmp w pll x4x8 pll off pll32 off osc lv d 1 lv d 0 wdg sw wdg halt default value 11111 100 1 1 1 0 1 1 1 1
device configuration st7lite20f2 ST7LITE25F2 st7lite29f2 152/166 doc id 8349 rev 5 15.1.2 option byte 1 opt7 = pllx4x8 pll factor selection. 0: pllx4 1: pllx8 opt6 = plloff pll disable 0: pll enabled 1: pll disabled (by-passed) opt5 = pll32off 32mhz pll disable 0: pll32 enabled 1: pll32 disabled (by-passed) opt4 = osc rc oscillator selection 0: rc oscillator on 1: rc oscillator off note: 1% rc oscillator available on st 7lite25 and st7lite29 devices only if the rc oscillator is selected, then to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nf, between the v dd and v ss pins as close as possible to the st7 device. opt3:2 = lvd[1:0] low voltage detection selection these option bits enable the lvd block with a selected threshold as shown in ta bl e 9 5 . opt1 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) opt0 = wdg halt watchdog reset on halt this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode table 95. lvd threshold configuration configuration lvd1 lvd0 lv d o f f 11 highest voltage threshold ( 4.1v) 1 0 medium voltage threshold ( 3.5v) 0 1 lowest voltage threshold ( 2.8v) 0 0
st7lite20f2 ST7LITE25F2 st7lite29f2 device configuration doc id 8349 rev 5 153/166 note: for further information, see clock management block diagram in figure 13 . 15.2 device ordering informatio n and transfer of customer code customer code is made up of the fastrom contents and the list of the selected options (if any). the fastrom contents are to be sent on diskette, or by electronic means, with the s19 hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmicroelectronics using the correctly completed option list appended on table 98: st7lite2 fastrom microcontroller option list . refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization will be pleased to provide detailed information on contractual points. table 96. list of valid option combinations operating conditions option bits v dd range clock source pll typ f cpu osc plloff pllx4x8 2.4v - 3.3v internal rc 1% (1) 1. configuration available on st 7lite25 and st7lite29 devices only off 0.7mhz @3v 0 1 1 x4 2.8mhz @3v 0 0 0 x8 ???? external clock or oscillator (depending on opt6:4 selection) off 0-4mhz 1 1 1 x4 4mhz 1 0 0 x8 ???? 3.3v - 5.5v internal rc 1% (1) off 1mhz @5v 0 1 1 x4 ???? x8 8mhz @5v 0 0 1 external clock or oscillator (depending on opt6:4 selection) off 0-8mhz 1 1 1 x4 ???? x8 8 mhz 1 0 1
device configuration st7lite20f2 ST7LITE25F2 st7lite29f2 154/166 doc id 8349 rev 5 note: contact st sales office for product availability. table 97. supported part numbers part number program memory (bytes) ram (bytes) data eeprom (bytes) temp. range package st7flite20f2b6 8k flash 384 ? -40c to 85c dip20 st7flite20f2m6 so20 st7flite25f2b6 ? dip20 st7flite25f2m6 so20 st7flite29f2b6 256 dip20 st7flite29f2m6 so20 st7flite29f2m7 so20 st7plite20f2b6 8k fastrom 384 ? -40c to 85c dip20 st7plite20f2m6 so20 st7plite25f2b6 ? dip20 st7plite25f2m6 so20 st7plite29f2b6 256 dip20 st7plite29f2m6 so20
st7lite20f2 ST7LITE25F2 st7lite29f2 device configuration doc id 8349 rev 5 155/166 table 98. st7lite2 fastrom microcontroller option list note: not all configuratio ns are available. see ta b l e 9 6 for authorized option byte combinations. customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone n o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/fastrom code (assigned by stmicroelectronics) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fastrom code must be sent in .s19 fo rmat. .hex extension cannot be processed. device type/memory size/package (check only one option): note: addresses 1000h, 1001h, ffdeh and ffdfh are reserved areas for st to program rccr0 and rccr1 (see section 7.1: internal rc oscillator adjustment ). conditioning (do not specify for dip package) [ ] tape & reel [ ] tube special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ " authorized characters are letters, di gits, '.', '-', '/' and spaces only. maximum character count: dip20/s020 (8 char. max) : _ _ _ _ _ _ _ _ watchdog selection: [ ] software activation [ ] hardware activation watchdog reset on halt: [ ] reset [ ] no reset lvd reset [ ] disabled [ ] enabled [ ] highest threshold [ ] medium threshold [ ] lowest threshold sector 0 size: [ ] 0.5k [ ] 1k [ ] 2k [ ] 4k read-out protection: [ ] disabled [ ] enabled flash write protection: [ ] disabled [ ] enabled clock source selection: [ ] resonator: [ ] vlp: very low power resonator (32 to 100 khz) [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] external clock: [ ] on osc1 [ ] on pb4 [ ] internal rc oscillator (st7plite25 and st7plite29 only) pll [ ] disabled [ ] pllx4 [ ] pllx8 pll32 [ ] disabled [ ] enabled comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply operating range in the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fastrom device 8k so20: [ ] st7plite20f2m6 [ ] st7plite25f2m6 [ ] st7plite29f2m6 [ ] st7flite29f2m7 dip20: [ ] st7plite20f2b6 [ ] st7plite25f2b6 [ ] st7plite29f2b6
device configuration st7lite20f2 ST7LITE25F2 st7lite29f2 156/166 doc id 8349 rev 5 15.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 microcontroller family. full de tails of tools available for the st7 from third party manufacturers can be obtained from the stmicroelectronics internet site: http//www.st.com. tools from these manufacturers include c compliers, evaluation tools, emulators and programmers. emulators two types of emulators are available from st for the st7lite2 family (refer to ta b l e 9 9 ): st7 dvp3 entry-level emulator offers a flexible and modular debugging and programming solution. so20 packages need a specific connection kit. st7 emu3 high-end emulator is delivered with everything (probes, teb, adapters etc.) needed to start emulating the st7lite2. to configure it to emulate other st7 subfamily devices, the active probe for the st7emu3 can be changed and the st7emu3 probe is designed for easy interchange of tebs (target emulation board). in-circuit debugging kit two configurations are available from st: st7flit2-ind/usb: low-cost in-circuit debugging kit from softec microsystems. includes stx-indart/usb board (usb port) and a specific demo board for st7flite29 (dip16) (a promotion package of 15 stflit2-ind/usb can be ordered with the following order code: stflit2-ind/15) stxf-indart/usb (a promotion package of 15 stxf-indart/usb can be ordered with the following order code: stxf-indart) flash programming tools st7-stick st7 in-circuit communication kit, a complete software/hardware package for programming st7 flash devices. it connec ts to a host pc parallel port and to the target board or socket board via st7 icc connector. icc socket boards provide an easy to use and flexible means of programming st7 flash devices. they can be connected to any tool that supports the st7 icc interface, such as st7 emu3, st7-dvp3, indart, st7-stick, or many third-party development tools. evaluation boards one evaluation tool is available from st: st7flit2-cos/com: streal time starter kit from cosmic software.
st7lite20f2 ST7LITE25F2 st7lite29f2 device configuration doc id 8349 rev 5 157/166 15.4 application notes table 99. stmicroelectronics development tools supported products emulation programming st7 dvp3 series st7 emu3 series icc socket board emulator connection kit emulator active probe & t.e.b. st7flite20 st7flite25 st7flite29 st7mdt10-dvp3 st7mdt10-20/ dvp st7mdt10-emu3 st7mdt10-teb st7sb10/123 (1) 1. add suffix /eu, /uk, /us for the power supply of your region. table 100. st7 application notes identification description application examples an1658 serial numbering implementation an1720 managing the read-out protection in flash microcontrollers an1755 a high resolution/precision thermometer using st7 and ne555 an1756 choosing a dali implementation strategy with st7dali an1812 a high precision, low cost, single supply adc for positive and negative input voltages example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communication between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wakeup on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinuso?d) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sour ces management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals
device configuration st7lite20f2 ST7LITE25F2 st7lite29f2 158/166 doc id 8349 rev 5 an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 pwm management for bldc motor drives using the st72141 an1130 an introduction to sensorless brushles s dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 emulated 16 bit slave spi an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer an1602 16-bit timing operations using st7262 or st7263b st7 usb mcus an1633 device firmware upgrade (dfu) implementation in st7 non-usb applications an1712 generating a high resolution sinewave using st7 pwmart an1713 smbus slave driver for st7 i2c peripherals an1753 software uart using 12-bit art an1947 st7mc pmac sine wave mo tor control software library general purpose an1476 low cost power supply for home appliances an1526 st7flite0 quick reference note an1709 emc design for st microcontrollers an1752 st72324 quick reference note product evaluation an 910 performance benchmarking an 990 st7 benefits versus industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1103 improved b-emf detection for low speed, low voltage with st72141 an1150 benchmark st72 vs pc16 table 100. st7 application notes (continued) identification description
st7lite20f2 ST7LITE25F2 st7lite29f2 device configuration doc id 8349 rev 5 159/166 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 applications to st72f264 an1604 how to use st7mdt1-train with st72f264 an2200 guidelines for migrating st7lite1x applications to st7flite1xb product optimization an 982 using st7 with ceramic resonator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1181 electrostatic dischar ge sensitive measurement an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage c apability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscillator an1605 using an active rc to wakeup the st7lite0 from power saving mode an1636 understanding and minimi zing adc conversion errors an1828 pir (passive infrared) detect or using the st7flite05/09/superlite an1946 sensorless bldc motor control and bemf sampling methods with st7mc an1953 pfc for st7mc starter kit an1971 st7lite0 microcontrolled ballast programming and tools an 978 st7 visual develop software key debugging features an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getting started with the st7 hiware c toolchain table 100. st7 application notes (continued) identification description
device configuration st7lite20f2 ST7LITE25F2 st7lite29f2 160/166 doc id 8349 rev 5 an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ programming) an1446 using the st72521 emulator to debug a st72324 target application an1477 emulated data eeprom with xflash memory an1478 porting an st7 panta project to codewarrior ide an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus an1576 in-application programming (iap) dr ivers for st7 hdflash or xflash mcus an1577 device firmware upgrade (dfu) implementation for st7 usb applications an1601 software implementation for st7dali-eval an1603 using the st7 usb device firmware upgrade development kit (dfu-dk) an1635 st7 customer rom code release information an1754 data logging program for testing st7 applications via icc an1796 field updates for flash based st 7 applications using a pc comm port an1900 hardware implementa tion for st7dali-eval an1904 st7mc three-phase ac induction motor control software library an1905 st7mc three-phase bldc motor control software library system optimization an1711 software techniques for compensating st7 adc errors an1827 implementation of sigma- delta adc with st7flite05/09 an2009 pwm management for 3-phase bldc motor drives using the st7fmc an2030 back emf detection during pwm on time by st7mc table 100. st7 application notes (continued) identification description
st7lite20f2 ST7LITE25F2 st 7lite29f2 important notes doc id 8349 rev 5 161/166 16 important notes 16.1 execution of btjx instruction when testing the address $ff with the "btjt" or "btjf" instructions, the cpu may perform an incorrect operation when the relative jump is negative and performs an address page change. to avoid this issue, including when using a c compiler, it is recommended to never use address $00ff as a variable (using the linker parameter for example). 16.2 adc conversion spurious results spurious conversions occur with a rate lower than 50 per million. su ch conversions happen when the measured voltage is just between 2 consecutive digital values. workaround a software filter should be implemented to remove erratic conversion results whenever they may cause unwanted consequences. 16.3 a/d converter accura cy for first conversion when the adc is enabled after being powered down (for example when waking up from halt, active-halt or setting the adon bit in the adccsr register), the first conversion (8-bit or 10-bit) accuracy does not meet the accuracy specified in the datasheet. workaround in order to have the accuracy specified in the datasheet, the first conversion after a adc switch-on has to be ignored. 16.4 negative injection impact on adc accuracy injecting a negative current on an analog input pins significantly reduces the accuracy of the ad converter. whenever necessary, the negative injection should be prevented by the addition of a schottky diode between the concerned i/os and ground. injecting a negative current on digital input pins degrades adc accuracy especially if performed on a pin close to adc channel in use. 16.5 clearing active interru pts outside interrupt routine when an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the cc register may be corrupted.
important notes st7lite20f2 ST7LITE25F2 st7lite29f2 162/166 doc id 8349 rev 5 concurrent interrupt context the symptom does not occur when the interrupts are handled normally, i.e. when: the interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine. the interrupt request is cleared (flag reset or interrupt mask) within any interrupt routine. the interrupt request is cleared (flag reset or interrupt mask) in any part of the code while this interrupt is disabled. if these conditions are not met, the symptom can be avoided by implementing the following sequence: perform sim and rim operation before and after resetting an active interrupt request ex: sim reset flag or interrupt mask rim 16.6 using pb4 as external interrupt pb4 cannot be used as an external interrupt in halt mode because the port pin pb4 is not active in this mode. 16.7 timebase 2 interrupt in slow mode timebase 2 interrupt is not available in slow mode.
st7lite20f2 ST7LITE25F2 st 7lite29f2 revision history doc id 8349 rev 5 163/166 17 revision history table 101. revision history date revision description of changes 30-aug-2004 3 updated figure 62. typical idd in wait vs. fcpu with correct data added data for fcpu @ 1mhz into section 13.4.1 supply current table. enabledprogramming capability for emu3, table 26 reset delay in section 11.1.3 on page 53 changed to 30s altered note 1 for section 13.2.3 on page 94 removing references to reset removed sentence relating to an effective change only after overflow for ck[1:0], page 61 mod00 replaced by 0ex in figure 37 on page 58 added note 2 related to exit from active halt, section 11.2.5 on page 60 changed section 11.4.2 on page 71 changed section 11.4.3.3 on page 74 added illegal opcode detection to page 1, section 7.6 on page 30 , section 12 on page 87 clarification of flash readout protection, section 4.5.1 on page 14 added note 4 and description relating to total percentage in error and amplifier output offset variation to the adc characteristics subsection and table, page 120 added note 5 and description relating to offset variation in temperature to adc characteristics subsection and table, page 120 f pll value of 1mhz quoted as typical instead of a minimum in section 13.3.4.1 on page 97 updated f sck in section 13.10.1 on page 115 to f cpu /4 and f cpu /2 correctedf cpu in slow and slow wait modes in section 13.4.1 on page 101 max values updated for adc accuracy, page 118 socket board development kit details added in table 27 on page 126 notes indicating that pb4 cannot be used as an external interrupt in halt mode, section 16.6 on page 132 and section 8.3 peripheral interrupts -removed ?optional? referring to v dd in figure 5 on page 13 -changed fmp_r option bit description in section 15.1 on page 124 -added ?clearing active interrupts outside interrupt routine? on page 132
revision history st7lite20f2 ST7LITE25F2 st7lite29f2 164/166 doc id 8349 rev 5 07-jul-2006 4 added 300k read/write cycles for eeprom on first page updated section 4.4 on page 21 and modified note 5 and figure 5 added note 2 in external interrupt control register (eicr) on page 41 and changed external interrupt function on page 63 modified read operation section in memory access on page 24 added note to section 7.1 on page 33 modified one note in section 7.1 on page 33 modified table on page 37 added note on illegal opcode reset to section 7.5.1 on page 38 added note to section 7.6.1 on page 40 changed note below figure 8 on page 26 and the last paragraph of access error handling on page 26 in section 11.2.6 on page 79 , modified description of oe bits in the pwmcr register (added ?after an overflow event?). added important note to section on page 94 changed section 13.2.1 on page 117 (f osc or f clkin replaced by f cpu and frequency values changed accordingly) added note 1 and modified note 3 in section on page 113 and section on page 122 and changed table titles added crystal and ceramic resonator oscillators on page 120 changed i s value and note 2 in section 12.7.1 on page 127 updated section 14.2 on page 149 added note to figure 67 on page 134 changed notes 1 and 2 to table 89 on page 144 and added r thja value for dip20 package changed figure 84 , figure 85 on page 140 (and notes) and removed emc protection circuitry in figure 85 on page 140 (device works correctly without these components) added note 2 to opt 4 (option byte 2) in section 15.1 on page 150 modified section 14.2 on page 149 changed section 15.3 on page 156 added section 16.7 on page 162 changed lticr reset value in table 3 on page 18 modified ?caution? in section 8.2 on page 46 replaced bit1 by bit2 for awuf bit in awucsr description in section 9.6.1 on page 61 modified section on page 63 changed order of section and section on page 87 and removed two paragraphs before section 11.3.4 on page 87 added note 3 to section 13.3.2 on page 121 modified section 12.9 on page 137 : changed t h(mo) and t v(mo) , as well as t su(ss ) and t h (ss ) values and added note 4. the change made to t su(ss ) and t h (ss ) values applies from silicon rev b of this product. changed t w(jit) value in section on page 113 and section on page 122 added note to section 12.4.2 on page 120 changed ltcsr2 reset value in section 11.3.6 on page 88 modified figure 84 and figure 85 on page 140 added note 1 to the max column in table on page 144 and modified the content of this note. table 101. revision history (continued) date revision description of changes
st7lite20f2 ST7LITE25F2 st 7lite29f2 revision history doc id 8349 rev 5 165/166 25-jun-2013 5 added temperature range in features on page 1 . added st7flite29f2m to table 97: supported part numbers and table 98: st7lite2 fastrom microcontroller option list . table 101. revision history (continued) date revision description of changes
st7lite20f2 ST7LITE25F2 st7lite29f2 166/166 doc id 8349 rev 5 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services describe d herein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automo- tive, automotive safety or medical ? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corre- sponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner wha tsoever, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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